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7.1.2.1
Exception Request and Detection
(1)
Exception occurrence
Exception sources include instruction execution by the CPU, memory accesses, and interrupt re-
quests from external interrupt pins or peripheral functions.
An exception occurs when the CPU executes an instruction that causes an exception or when an er-
ror condition occurs during instruction execution.
An exception also occurs by an instruction fetch from the Execute Never (XN) region or an ac-
cess violation to the Fault region.
An interrupt request is generated from an external interrupt pin or peripheral function.For inter-
rupts that are used for releasing a standby mode, relevant settings must be made in the clock genera-
tor.For details, refer to "7.5 Interrupts".
(2)
Exception detection
If multiple exceptions occur simultaneously, the CPU takes the exception with the highest priority.
Table 7-1 shows the priority of exceptions. "Configurable" means that you can assign a priority lev-
el to that exception. Memory Management, Bus Fault and Usage Fault exceptions can be enabled or
disabled. If a disabled exception occurs, it is handled as Hard Fault.
Table 7-1 Exception Types and Priority
No.
Exception type
1
Reset
2
Non-Maskable Interrupt
3
Hard Fault
4
Memory Management
5
Bus Fault
6
Usage Fault
7 to 10 Reserved
11
SVCall
12
Debug Monitor
13
Reserved
14
PendSV
15
SysTick
16 or
External Interrupt
more
Note 1: This product does not contain the MPU.
Note 2: External interrupts have different sources and numbers in each product. For details, see
"7.5.1.5 List of Interrupt Sources".
Priority
−3 (highest)
Reset pin, WDT, POR, OFD, VLTD, SYSRESETREQ
−2
WDT
Fault that cannot activate because a higher-priority fault is being han-
−1
dled or it is disabled
Exception from the Memory Protection Unit (MPU) (Note 1)
Configurable
Instruction fetch from the Execute Never (XN) region
Configurable
Access violation to the Hard Fault region of the memory map
Undefined instruction execution or other faults related to instruction ex-
Configurable
ecution
−
Configurable
System service call with SVC instruction
Configurable
Debug monitor when the CPU is not faulting
−
Configurable
Pendable system service request
Configurable
Notification from system timer
Configurable
External interrupt pin or peripheral function (Note 2)
Page 77
TMPM3V6/M3V4
Description
2019-02-06
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