Toshiba TX03 Series Manual page 375

32 bit risc microcontroller
Table of Contents

Advertisement

15.4.1.4
Enabling Reception
By enabling the RMCxREN <RMCREN> after configuring the RMCxRCR1, RMCxRCR2,
RMCxRCR3 and RMCxRCR4 registers, RMC is ready for reception. Detecting a leader initiates reception.
Note: Changing the configurations of the RMCxRCR1, RMCxRCR2, RMCxRCR3 and RMCxRCR4 regis-
ters during reception may harm their proper operation. Be careful if you change them during reception.
15.4.1.5
Stopping Reception
RMC stops reception by clearing the RMCxREN <RMCREN> to "0" (reception disabled).
Clearing this bit during reception stops reception immediately and the received data is discarded.
15.4.1.6
Receiving Remote Control Signal without Leader in Waiting Leader
Setting RMCxRCR2 <RMCLD> enables RMC to receive signals with or without a leader.
By setting RMCxRCR2 <RMCLD>, RMC starts receiving data if it recognizes a signal of which
"Low" width is shorter than a maximum "Low" width of leader detection specified in the RMCxRCR1
<RMCLLMAX[7:0]>. RMC keeps receiving data until the final data bit is received.
If RMCxRCR2 <RMCLD> is enabled, the same settings of error detection, reception completion and da-
ta bit determination of 0 or 1 are applied regardless of whether a signal has a leader or not.
Thus receivable remote control signals are limited.
Waiting for leader
Figure 15-8 Receiving Remote Control Signal without Leader in Waiting Leader (In the case
Leader waveform
RMC starts receiving data by receiving a signal which
is less than the minimum low pulse width.
Maximum data bit cycle is detected if a signal stays
low shorter than specified and longer than a maximum
data bit cycle.
Minimum low width <RMCLLMIN[7:0]>
Maximum data bit cycle <RMCDMAX[7:0]>
of RMCxRCR2<RMCLD>="1")
Page 353
TMPM3V6/M3V4
2019-02-06

Advertisement

Table of Contents
loading

This manual is also suitable for:

Tmpm3v6Tmpm3v4

Table of Contents