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7.
Exceptions
7.6
Exception/Interrupt-Related Registers
7.6.2.8
bit symbol
After reset
bit symbol
After reset
bit symbol
ENDIANESS
After reset
bit symbol
After reset
Bit
Bit Symbol
31-16
VECTKEY
(Write)/
VECTKEY-
STAT(Read)
15
ENDIANESS
14-11
−
10-8
PRIGROUP
7-3
−
2
SYSRESET
REQ
1
VECTCLR
ACTIVE
0
VECTRESET
Note 1: Little-endian is the default memory format for this product.
Note 2: When <SYSRESETREQ> is output, warm reset is performed on this product. <SYSRESETREQ> is
2019-02-06
Application Interrupt and Reset Control Register
31
30
0
0
23
22
0
0
15
14
-
0
0
7
6
-
-
0
0
Type
R/W
Register key
[Write] Writing to this register requires 0x5FA in the <VECTKEY> field.
[Read] Read as 0xFA05.
R/W
Endianness bit:(Note1)
1: big endian
0: little endian
R
Read as 0.
R/W
Interrupt priority grouping
000: seven bits of pre-emption priority, one bit of subpriority
001: six bits of pre-emption priority, two bits of subpriority
010: five bits of pre-emption priority, three bits of subpriority
011: four bits of pre-emption priority, four bits of subpriority
100: three bits of pre-emption priority, five bits of subpriority
101: two bits of pre-emption priority, six bits of subpriority
110: one bit of pre-emption priority, seven bits of subpriority
111: no pre-emption priority, eight bits of subpriority
The bit configuration to split the interrupt priority register <PRI_n> into pre-emption priority and sub priority.
R
Read as 0.
R/W
System Reset Request.
1=CPU outputs a SYSRESETREQ signal. (note2)
R/W
Clear active vector bit
1: clear all state information for active NMI, fault, and interrupts
0: do not clear.
This bit self-clears.
It is the responsibility of the application to reinitialize the stack.
R/W
System Reset bit
1: reset system
0: do not reset system
Resets the system, with the exception of debug components (FPB, DWT and ITM) by setting "1" and this
bit is also zero cleared.
cleared by warm reset.
29
28
27
VECTKEY/VECTKEYSTAT
0
0
0
21
20
19
VECTKEY/VECTKEYSTAT
0
0
0
13
12
11
-
-
-
0
0
0
5
4
3
-
-
-
0
0
0
Function
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TMPM3V6/M3V4
26
25
0
0
18
17
0
0
10
9
PRIGROUP
0
0
2
1
SYSRESET
VECTCLR
VECTRESET
REQ
ACTIVE
0
0
24
0
16
0
8
0
0
0
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