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16.4.7
ADCMPCR1(Monitoring Setting Register 1)
After fixing the conversion result, the interrupt signal (INTADCP) is generated.
31
bit symbol
-
After reset
0
23
bit symbol
-
After reset
0
15
bit symbol
-
After reset
0
7
bit symbol
CMP1EN
After reset
0
Bit
Bit Symbol
Type
31-12
-
R
11-8
CMPCNT1[3:0]
R/W
7
CMP1EN
R/W
6-5
-
R
4
ADBIG1
R/W
3-0
REGS1[3:0]
R/W
30
29
28
-
-
-
0
0
0
22
21
20
-
-
-
0
0
0
14
13
12
-
-
-
0
0
0
6
5
4
-
-
ADBIG1
0
0
0
Read as "0".
Comparison count for determining the result
0: After every comparison
1: After two comparisons
・
・
15: After 16 comparisons
The ADCMPCR0 and ADCMPCR1 registers are used to enable or disable comparison between an AD
conversion result and the specified comparison value, to select the register to be compared with an AD
conversion result and to set how many times comparison should be performed to determine the result.
Monitoring function
0:Disable
1:Enable
By setting <CMP1EN>="0"(disable), accumulated number of decision counts is cleared.
Read as "0".
Comparison condition
0:Larger than or equal to compare register
1:Smaller than or equal to compare register
Compares whether a result of analog input is larger or smaller than the compare register.
Every time AD conversion, which is set in the <REGS1[3:0]>, is complete, large/small decision is per-
formed.
If the result is matched the setting in <ADBIG1>, the counter increments.
AD conversion result register to be compared
0000: ADREG0
0100: ADREG4
0001: ADREG1
0101: ADREG5
0010: ADREG2
0110: ADREG6
0011: ADREG3
0111: ADREG7
Page 365
27
26
25
-
-
-
0
0
0
19
18
17
-
-
-
0
0
0
11
10
9
CMPCNT1
0
0
0
3
2
1
REGS1
0
0
0
Function
1000: ADREG8
1001: ADREG9
1010: ADREG10
1011: ADREG11
TMPM3V6/M3V4
24
-
0
16
-
0
8
0
0
0
2019-02-06
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