Toshiba TX03 Series Manual page 350

14. Synchronous Serial Port (SSP)
14.6 Frame Format
14.6.2 SPI frame format
The SPI interface has 4 lines. SPFSS is used for slave selection. One of the main features of the SPI for-
mat is that the <SPO> and <SPH> bits in the SSPCR0 register can be used to set the SPCLK operation timing.
SSPCR0 <SPO> is used to set the level at which SPCLK in idle state is held.
SSPCR0 <SPH> is used to select the clock edge at which data is latched.
Figure 14-4 SPI frame format (single transfer, <SPO>="0" & <SPH>="0")
Figure 14-5 SPI frame format (continuous transfer,<SPO>="0" & <SPH>="0")
Note 1: When transmission is disable, SPDO terminal doesn't output and is high impedance status. This terminal needs
Note 2: SPDI terminal is always input and internal gate is open. In case of transmission signal will be high impedance sta-
2019-02-06
SSPCR0<SPO>
0 "Low" state
1 "High" state
SPCLK
SPFSS
SPDO
Hi-Z(Note1
SPDI
Hi-Z(Note2)
SPCLK
SPFSS
SPDO
LSB
SPDI
LSB
Hi-Z(Note2)
to add suitable pull-up/down resistance to valid the voltage level.
tus, this terminal needs to add suitable pull-up/down resistance to valid the voltage level.
SSPCR0<SPH>
Capture data at the 1st clock edge.
Capture data at the 2nd clock edge.
MSB LSB
MSB
LSB
MSB LSB
MSB LSB
Hi-Z(Note2)
to 16bit
Page 328
TMPM3V6/M3V4
Hi-Z(Note1
Hi-Z(Note2
MSB
MSB