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18.
Power-on-Reset Circuit (POR)
18.2
Function
18.2
Function
At power-on, a power-on detection signal generates while power supply voltage is lower than the releasing volt-
age. Power-on detection signal is released at the timing when RVDD5 is over 3.0 ±0.2 V.
When the power-on detection signal is released and the VLTD reset signal is also released, the power-on counter
starts to operate. After waiting time (approximately 0.9 ms) has elapsed, the internal reset signal is released.
During the internal reset signal generation, the CPU and the peripheral functions are reset.
When a reset input pin is not used, supply voltage must be raised to the VLTD detect voltage until the internal
reset releasing. If power supply voltage does not reach to the VLTD detect voltage during this period,
TMPM3V6/3V4 cannot operate properly.
Since it operate continuously with the voltage detection circuit (VLTD), please refer to the voltage detection
circuit (VLTD) section.
Power-on-reset release voltage (VPORH)
Note: Since the power-on releasing voltage and the power-on reset detection voltage relatively change,the detec-
tion voltage is never reversed.
Note: Due to the fluctuation of supply voltage, the power-on reset circuit may not operate properly. Users should
give due consideration based on the electrical characteristic in the device designing.
2019-02-06
Operation voltage range
Power-on detect signal
"Low" active)
Reset detect signal
"Low" active)
Power-on counter
Internal reset signal
"Low" active)
Figure 18-2 Power-on-reset operation timing
Symbol
Parameter
tDVDD
Rising time of power line
VPORH
Power-on Reset releasing voltage
VPORL
Power-on Reset detection voltage
tPORDT1
Power-on Reset release response time
detect voltage
4.1V±0.2V
Internal 1.5V power supply voltage
tDVDD
Min
0.1
2.8
2.6
Page 416
TMPM3V6/M3V4
Power supply voltage
Typ
Max
Unit
-
500
ms
3
3.2
V
2.8
3.0
V
30
μs
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