Table of Contents
Advertisement
11.
Universal Asynchronous Receiver-Transmitter Circuit (UART)
11.3
Registers
11.3.15
UARTxHCCR (50% Duty Control Register)
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Bit
Bit symbol
31-8
−
7
HCLPB
6-4
HCZR[2:0]
3
-
2
HCST
1
HCMD
0
HCCR
Note: The loop-back test control is the test function in the development stage. Do not use for the final products.
2019-02-06
31
30
-
-
0
0
23
22
-
-
0
0
15
14
-
-
0
0
7
6
HCLPB
HCZR
0
0
Type
R
Write as "0".
R/W
Loop back test enable (Note)
0: Disable
1: Enable
R/W
"0" period detection control
000: Reserved
001: 1/16 width more than "0" detection
010: 2/16 width more than "0" detection
011: 3/16 width more than "0" detection
100: 4/16 width more than "0" detection
101: 5/16 width more than "0" detection
110: 6/16 width more than "0" detection
111: 7/16 width more than "0" detection
R/W
Write as "0".
R/W
Terminal selection to start the start bit
0: UTxTXD50A
1: UTxTXD50B
R/W
Transmission terminal mode selection
0: 1 terminal mode
1: 2 terminal mode
R/W
50% duty mode enable
0: Disable
1: Enable
29
28
27
-
-
-
0
0
0
21
20
19
-
-
-
0
0
0
13
12
11
-
-
-
0
0
0
5
4
3
-
1
1
0
Function
Page 202
TMPM3V6/M3V4
26
25
-
-
0
0
18
17
-
-
0
0
10
9
-
-
0
0
2
1
HCST
HCMD
HCCR
0
0
24
-
0
16
-
0
8
-
0
0
0
2019-02-06
Advertisement
Table of Contents
