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7.5.2
Interrupt Handling
7.5.2.1
Flowchart
The following shows how an interrupt is handled.
In the following descriptions,
handling.
Processing
Settings for detection
Settings for sending interrupt
signal
Interrupt generation
Not clearing
standby mode
Clearing
standby mode
CG detects interrupt
(clearing standby mode)
CPU detects interrupt
CPU handles interrupt
indicates hardware handling.
Details
Set the relevant NVIC registers for detecting interrupts.
Set the clock generator as well if each interrupt source is used to clear a stand-
by mode.
οCommon setting
NVIC registers
οSetting to clear standby mode
Clock generator
Execute an appropriate setting to send the interrupt signal depending on the in-
terrupt type.
οSetting for interrupt from external pin
Port
οSetting for interrupt from peripheral function
Peripheral function (See the chapter of each peripheral function for details.)
An interrupt request is generated.
Interrupt lines used for clearing a standby mode are connected to the CPU
via the clock generator.
The CPU detects the interrupt.
If multiple interrupt requests occur simultaneously, the interrupt request with
the highest priority is detected according to the priority order.
The CPU handles the interrupt.
The CPU pushes register contents to the stack before entering the ISR.
Page 89
TMPM3V6/M3V4
indicates software
See
"7.5.2.2 Preparation"
"7.5.2.3 Detection by
Clock Generator"
"7.5.2.4 Detection by
CPU"
"7.5.2.5 CPU pro-
cessing"
2019-02-06
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