Toshiba TX03 Series Manual page 259

12.6.3 Transmit/Receive Buffer and FIFO
12.6.3.1 Configuration
Figure 12-4 shows the configuration of transmit buffer, receive buffer and FIFO.
Appropriate settings are required for using buffer and FIFO. The configuration may be predefined depend-
ing on the mode.
RXDx
Receive FIFO First stage
Figure 12-4 The Configuration of Buffer and FIFO
12.6.3.2 Transmit/Receive Buffer
Transmit buffer and receive buffer are double-buffered. The buffer configuration is specified by
SCxMOD2<WBUF>.
When serial channel is operated as receive, if it is operated as clock input mode in the I/O interface
mode or it is operated as the UART mode, it's double buffered regardless of <WBUF> settings.
In other modes, it's according to the <WBUF> settings.
Table 12-5 shows correlation between modes and buffers.
Table 12-5 Mode and buffer Composition
Receive shift register
Receive buffer
Second stage
Third stage
Fourth stage
Mode
Transmit
UART mode
Receive
Transmit
I/O interface mode
(Clock input mode)
Receive
Transmit
I/O interface mode
(Clock output mode)
Receive
Page 237
Transmit shift register
Transmit buffer
Transmit FIFO First stage
Second stage
Third stage
Fourth stage
SCxMOD2<WBUF>
"0" "1"
Single Double
Double Double
Single Double
Double Double
Single Double
Single Double
TMPM3V6/M3V4
TXDx
2019-02-06