Single Boot Mode; Figure 2.4 Single Boot Mode - Toshiba TXZ+ Series Reference Manual

2.2.1.2. Single Boot Mode

RAMP(ch0)
CRC
CG
IB(INTIF)
IMN(INTIF)
IA(INTIF)
RLM
LVD
ADC
OPAMP
T32A
UART
PORT
TRM
OFD
A-PMD
A-ENC32
A-VE+
Flash(SFR)
APB: Advanced Peripheral Bus, AO: 8bit-Bus for Backup domain, IO: 32bit-Bus for Main domain
S0
M0
M1
M2
M3
(Note)
M4
M5
M6
M7
APB
M8
IO
M9
S0
Clock
Synchronous
circuit
DMAC
SS0
SM0
SM1
SM2
SM3
AO
SM4
APB
SM5
SM6
APB
SM7
SM8
IO
SS0
Note:Access to DataFlash is only for DMAC

Figure 2.4 Single Boot Mode

Clock Control and Operation Mode
Cortex-M4(with FPU)
S-Bus D-Bus I-Bus
S1 S2 S3
S1 S2 S3
NBDIF
SS1 SS2
SM0
SM1
SM2
SM3
SM4
SM5
SM6
SM7
SM8
SS1 SS2
48 / 64
TMPM4K Group(2)
M0
Code Flash
M1
M2
M3 Data Flash
M4 Boot ROM
M5 RAM0
M6 RAM1
M7
M8
M9
Clock
Synchronous
circuit
RAM2
TSPI
I2C
APB
EI2C
DNF
APB
TRGSEL
SIWDT
NBDIF
RAMP(ch1)
DMAC(SFR)
TXZ+ Family
2021-06-15
Rev. 1.1