Toshiba TX03 Series Manual page 264

12. Serial Channel with 4bytes FIFO (SIO/UART)
12.9 Receive
12.9.3.2
buffer full flag is cleared immediately. An interrupt will be generated according to the SCxRFC<RIL[1:0]
>.
SCxMOD1<FDPX[1:0]> = "01"
SCxFCNF<RFST><TFIE><RFIE>
<RXTXCNT><CNFG> = "10111"
SCxRFC<RIL[1:0]> = "00"
SCxRFC<RFCS><RFIS> = "01"
SCxMOD0<RXE>. When the data is stored all in the receive shift register, receive buffer and receive
FIFO, SCxMOD0<RXE> is automatically cleared and the receive operations completed.
sible to receive a data continuously by reading the data in the FIFO.
Receive shift register
Receive buffer
RX FIFO The first stage
The second stage
The third stage
The fourth stage
RX Interrupt (INTRXx)
SCxMOD2<RBFLL>
SCxMOD0<RXE>
2019-02-06
Receive FIFO Operation
When FIFO is enabled, the received data is moved from receive buffer to receive FIFO and the receive
Note: When the data with parity bit are received in UART mode by using the FIFO, the parity error
flag is shown the occurring the parity error in the received data.
The configurations and operations in the half duplex Receive mode are described as follows.
:Transfer mode is set to half duplex mode
:Automatically inhibits continuous reception after reaching the fill level.
:The number of bytes to be used in the receive FIFO is the same as the interrupt generation fill lev-
el.
:The fill level of FIFO in which generated receive interrupt is set to 4 bytes
:Clears receive FIFO and sets the condition of interrupt generation.
After setting of the above FIFO configuration, the data reception is started by writing "1" to the
In the above condition, if the continuous reception after reaching the fill level is enabled, it becomes pos-
DATA1
Figure 12-6 Receive FIFO Operation
DATA2 DATA3 DATA4
DATA1 DATA2 DATA3
DATA1 DATA2 DATA3
DATA1 DATA2
DATA1
Page 242
TMPM3V6/M3V4
DATA5 DATA6
DATA4 DATA5 DATA5
DATA4 DATA4 DATA4
DATA3 DATA3 DATA3
DATA2 DATA2 DATA2
DATA1 DATA1 DATA1