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13.7.2
SBICR1(Control register 1)
31
bit symbol
-
After reset
0
23
bit symbol
-
After reset
0
15
bit symbol
-
After reset
0
7
bit symbol
SIOS
SIOINH
After reset
0
Bit
Bit Symbol
Type
31-8
-
R
7
SIOS
R/W
6
SIOINH
R/W
5-4
SIOM[1:0]
R/W
3
-
R
2-0
SCK[2:0]
R/W
Note 1: After a reset, the <SCK[0]> bit is read as "1". However, if the SIO mode is selected at the SBICR2 regis-
ter, the initial value is read as "0". In this document, the value written in the column "after reset" is the val-
ue after setting the SIO mode in the initial state. The descriptions of the SBICR2 register and the SBISR reg-
ister are the same.
Note 2: Set <SIOS> to "0" and <SIOINH> to "1" before programming the transfer mode and the serial clock.
30
29
28
-
-
-
0
0
0
22
21
20
-
-
-
0
0
0
14
13
12
-
-
-
0
0
0
6
5
4
SIOM
0
0
0
Read as 0.
Transfer Start/Stop
0: Stop
1: Start
Transfer
0: Continue
1: Forced termination
Select transfer mode
00: Transmit mode
01: Reserved
10:Transmit/receive mode
11:Receive mode
Read as 1.
On writing <SCK[2:0]>: Select serial clock frequency. (Note 1)
000
n = 3
001
n = 4
010
n = 5
011
n = 6
100
n = 7
101
n = 8
110
n = 9
111
−
Page 297
27
26
-
-
0
0
19
18
-
-
0
0
11
10
-
-
0
0
3
2
-
1
0
Function
2.5 MHz
1.25 MHz
625 kHz
System clock: fsys
313 kHz
Clock gear: fc/1
156 kHz
fsys/2
78 kHz
Frequency =
39 kHz
External clock
TMPM3V6/M3V4
25
24
-
-
0
0
17
16
-
-
0
0
9
8
-
-
0
0
1
0
SCK
0
0(Note 1)
40MHz
( =
)
[Hz]
n
2
2019-02-06
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