Toshiba TX03 Series Manual page 142

7. Exceptions
7.6 Exception/Interrupt-Related Registers
(1)
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Note 1: The active level specified by <EMCGx[2:0]> varies depending on the interrupt request. Refer to Table 7-4.
Note 2: <EMSTx> is valid only when <EMCGx[2:0]> is set to "100" for both on rising and falling edges. In the other cases,
the value is undefined. The active level used for release of low-power consumption mode can be checked by reading
<EMSTx>. If interrupts are cleared with the CGICRCG register, <EMSTx> is also cleared.
Note 3: Do not specify <INTxEN> when the edge is selected. Select the edge first and then specify <INTxEN>. Setting them si-
multaneously is prohibited.
Note 4: "0" is read from bits 31, 23, 15 and 7.
Note 5: Undefined value is read from bits 25, 17, 9 and 1.
(2)
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Note 1: The active level specified by <EMCGx[2:0]> varies depending on the interrupt request. Refer to Table 7-4.
Note 2: <EMSTx> is valid only when <EMCGx[2:0]> is set to "100" for both on rising and falling edges. In the other cases,
the value is undefined. The active level used for release of low-power consumption mode can be checked by reading
<EMSTx>. If interrupts are cleared with the CGICRCG register, <EMSTx> is also cleared.
Note 3: Do not specify <INTxEN> when the edge is selected. Select the edge first and then specify <INTxEN>. Setting them si-
multaneously is prohibited.
Note 4: "0" is read from bits 31, 23, 15 and 7.
Note 5: Undefined value is read from bits 25, 17, 9 and 1.
2019-02-06
CGIMCGA (CG Interrupt Mode Control Register A)
31 30 29
- EMCG3
0 0 1
23 22 21
- EMCG2
0 0 1
15 14 13
- EMCG1
0 0 1
7 6 5
- EMCG0
0 0 1
CGIMCGB(CG Interrupt Mode Control Register B)
31 30 29
- EMCG7
0 0 1
23 22 21
- EMCG6
0 0 1
15 14 13
- EMCG5
0 0 1
7 6 5
- EMCG4
0 0 1
28 27
EMST3
0 0
20 19
EMST2
0 0
12 11
EMST1
0 0
4 3
EMST0
0 0
28 27
EMST7
0 0
20 19
EMST6
0 0
12 11
EMST5
0 0
4 3
EMST4
0 0
Page 120
TMPM3V6/M3V4
26 25 24
- INT3EN
0 undefined 0
18 17 16
- INT2EN
0 undefined 0
10 9 8
- INT1EN
0 undefined 0
2 1 0
- INT0EN
0 undefined 0
26 25 24
- INT7EN
0 undefined 0
18 17 16
- INT6EN
0 undefined 0
10 9 8
- INT5EN
0 undefined 0
2 1 0
- INT4EN
0 undefined 0