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12.
Serial Channel with 4bytes FIFO (SIO/UART)
12.6
Clock Control
(2)
Baud rate calculation
Transfer rate =
2019-02-06
Transfer clock in the UART mode
Table 12-4 shows the clock selection in the UART mode. In the UART mode, selected clock is divi-
ded by 16 in the receive counter or the transmit counter before use.
Table 12-4 Clock Selection in UART Mode
Mode
SCxMOD0<SM[1:0]>
UART Mode
("01", "10", "11")
To use SCLKx pin input, the following conditions must be satisfied.
- SCLK cycle > 2/fsys
To enable the timer output, a timer flip-flop output inverts when the value of the counter and that
of TBxRG1 match. The SIOCLK clock frequency is "Setting value of TBxRG1 × 2".
Baud rates can be obtained by using the following formula.
Clock frequency selected by CGSYSCR<PRCK[1:0]>
(TBxRG1 × 2) × 2 × 16
Clock selection
SCxMOD0<SC[1:0]>
"00" : TMRB output
"01" : Baud rate generator
"10" : fsys
"11" : SCLKx pin input
In the case the tim er prescaler clock Φ T 1
(2div ition ratio) is selected.
O ne clock cycle is a period that the tim er flip-flop
is inv erted twice.
Page 236
TMPM3V6/M3V4
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