Toshiba TX03 Series Manual page 459

21.4.2 Internal reset generation
Figure 21-3 shows the internal reset generation (WDMOD<RESCR>="1").
MCU is reset by the overflow of the binary counter. In this case, reset status continues for 32 states. A
clock is initialized so that input clock (fsys) is the same as a internal high-speed frequency clock (fosc). This
means fsys = fosc.
WDT counter
INTWDT
Internal reset
WDTOUT
Overflow
n
Figure 21-3 Internal reset generation
Page 437
32-state
TMPM3V6/M3V4
2019-02-06