Toshiba TX03 Series Manual page 263

12.9 Receive
12.9.1 Receive Counter
The receive counter is a 4-bit binary counter and is up-counted by SIOCLK.
In the UART mode, sixteen SIOCLK clock pulses are used in receiving a single data bit and the data sym-
bol is sampled at the eighth pulse.
12.9.2 Receive Control Unit
12.9.2.1 I/O interface mode
In the clock output mode with SCxCR <IOC> set to "0", the RXDx pin is sampled on the rising edge
of SCLKx pin.
In the clock input mode with SCxCR <IOC> set to "1", the RXDx pin is sampled on the rising or fall-
ing edge of SCLKx pin depending on the SCxCR <SCLKS>.
12.9.2.2 UART Mode
The receive control unit has a start bit detection circuit, which is used to initiate receive operation
when a normal start bit is detected.
12.9.3 Receive Operation
12.9.3.1 Receive Buffer
The received data is stored by 1 bit in the receive shift register. When a complete set of bits has been stor-
ed, the interrupt INTRXx is generated.
When the double buffer is enabled, the data is moved to the receive buffer (SCxBUF) and the receive buf-
fer full flag (SCxMOD2<RBFLL>) is set to "1". The receive buffer full flag is cleared to "0" by reading
the receive buffer. When the double buffer is disabled, the receive buffer full flag has no meaning.
Receive shift register
Receive buffer
Receive interrupt(INTRXx)
SCxMOD2<RBFLL>
DATA 1
DATA 1
Figure 12-5 Receive Buffer Operation
Page 241
TMPM3V6/M3V4
Receive buffer read
2019-02-06