Toshiba TX03 Series Manual page 332

14. Synchronous Serial Port (SSP)
14.2 Block Diagram
14.2 Block Diagram
fsys
INTSSP
2019-02-06
Clock
prescaler
Write data
[15:0]
APB interface
and
register
Read data
[15:0]
Interrupt request
Figure 14-1 SSP block diagram
SSPCLKDIV
Tx/Rx param
16bit 8
Transmit
TXD[15:0]
FIFO
RXD[15:0]
16bit 8
Receive
FIFO
Transmission buffer
processing request
Reception buffer
processing request
Timeout
Overrun
Page 310
TMPM3V6/M3V4
SPDI
Transmission/
SPDO
Reception logic
SPCLK
SPFSS
FIFO status
and
interrupt generation