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10.
16-bit Timer / Event Counters (TMRB)
10.4
Registers
10.4.5
TBxMOD (Mode register)
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
Bit Symbol
31-7
−
6
TBRSWR
5
TBCP
4-3
TBCPM[1:0]
2
TBCLE
1-0
TBCLK[1:0]
Note 1: Do not modify TBxMOD during operating TMRBx.
Note 2: Specifications are different depending on the product. For details, refer to "Product Information".
2019-02-06
31
30
29
-
-
-
0
0
0
23
22
21
-
-
-
0
0
0
15
14
13
-
-
-
0
0
0
7
6
5
-
TBRSWR
TBCP
0
0
1
Type
R
Read as "0".
R/W
Controls the timing to write to timer registers 0 and 1 when double buffering is enabled.
0: Timer registers 0 and 1 can be written separately, even in case writing preparation is ready for only one
resister.
1: In case both resisters are not ready to be written, Timer registers 0 and 1 can not be written
W
Capture control by software
0: Capture by software
1: Don't care
When "0" is written, the capture register 0 (TBxCP0) takes count value.
Read as "1".
R/W
Capture timing (Note2)
00: Disable
01: TBxIN↑
Takes count values into capture register 0 (TBxCP0) upon rising of TBxIN pin input.
10: TBxIN↑ TBxIN↓
Takes count values into capture register 0 (TBxCP0) upon rising of TBxIN pin input.
Takes count values into capture register 1 (TBxCP1) upon falling of TBxIN pin input.
11: TBxOUT↑ TBxOUT↓
Takes count values into capture register 0 (TBnCP0) upon rising of 16-bit timer match output (TBxOUT)
and into capture register 1 (TBnCP1) upon falling of TBxOUT.
R/W
Up-counter control
0: Disables clearing of the up-counter.
1: Enables clearing of the up-counter.
Clears and controls the up-counter.
When "0" is written, it disables clearing of the up-counter. When "1" is written, it clears up counter when
there is a match with Timer Regsiter1 (TBxRG1).
R/W
Selects the TMRBx source clock.
00: TBxIN pin input
01: φT1
10: φT4
11: φT16
28
27
-
-
0
0
20
19
-
-
0
0
12
11
-
-
0
0
4
3
TBCPM
0
0
Function
Page 164
TMPM3V6/M3V4
26
25
-
-
0
0
18
17
-
-
0
0
10
9
-
-
0
0
2
1
TBCLE
TBCLK
0
0
24
-
0
16
-
0
8
-
0
0
0
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