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6.
Clock/Mode control
6.3
Clock control
6.3.3
Clock system Diagram
Figure 6-1 shows the clock system diagram.
The input clocks to selector shown with an arrow are set as default after reset.
CGOSCCR<XEN2>
Starts oscillation after reset
Internal High-Speed
oscillator
X1
External High-Speed
oscillator
X2
CGOSCCR<XEN >
Stops oscillation after reset
XT1
External Low-Speed
oscillator
XT2
CGOSCCR<XTEN>
Stops oscillation after reset
fperiph
2019-02-06
CGOSCCR<WUEON>
CGOSCCR<WUODR[11:0]>
CGOSCCR<WUODRL[1:0]>
Warming-up timer
CGOSCCR
<WUPSEL1>
CGOSCCR
<WUPSEL2>
f
IHOSC
CGOSCCR
<OSCSEL>
f
EHOSC
OFD
fs
1/2
1/4
1/8
1/16
1/32
CGSYSCR
<PRCK[2:0]>
fsys
fs
Figure 6-1 Clock Block Diagram
CGPLLSEL
<PLLSEL>
CGOSCCR<PLLON>
Stops oscillation after reset
f
PLL
PLL
1/2
fosc
1/32
CGSYSCR
<FPSEL1>
T0
1/2
CGSYSCR
<SCOSEL[1:0]>
Page 54
FCSTOP
CGSYSCR
CGSYSCR<FCSTOP>
<FPSEL0>
Starts oscillation after reset
f gear
fc
1/4
1/8
1/16
CGSYSCR
CGCKSEL
<GEAR[2:0]>
<SYSCK>
SysTick external reference clock
CPU
Peripheral I/O prescaler input
TMRB, SIO/UART
AHB-Bus I/O
CPU, ROM, RAM,
BOOT ROM
APB-Bus I/O
SSP, UART
IO-Bus I/O
TMRB, WDT, RTC,
SIO/UART, I2C/SIO, RMC, ADC,
PORT
RTC Prescaler input
RMC Sampling clock
SCOUT
TMPM3V6/M3V4
AD conversion clock
<ADCLK>
fperiph
(to Peripheral I/O)
fsys
fs
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