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CHAPTER 3 CPU AND CONTROL UNITS
(2) The RP referred to by the RET:D instruction is not affected even when the instruction in the delay slot
updates the RP.
[Example]
RET:D
MOV
...
(3) The flag referred to by the Bcc:D rel instruction is not affected by the instruction in the delay slot.
[Example]
ADD
BC:D
ANDCCR#0
...
(4) When the instruction in the delay slot of the CALL:D instruction refers the RP, the content of the
update made by the CALL:D instruction is read.
[Example]
CALL:D Label
MOV
...
●
Restrictions
(1) Instructions that can be executed in a delay slot
The instructions satisfying the following conditions can be executed in the delay slot:
•
One-cycle instruction
•
Non-branch instruction
•
Instruction not affecting the operation even when the execution order is changed
The "one-cycle instruction" means an instruction marked with "1", "a", "b", "c", or "d" in the "CYCLE"
column (the number of cycles required) in the instruction list in Appendix E.
(2) Step trace trap
A step trace trap does not occur between the execution of a branch instruction with delay slot and the
delay slot.
(3) Interrupt or NMI
No interrupt or NMI is accepted between the execution of a branch instruction with delay slot and the
delay slot.
(4) Undefined instruction exception
If an undefined instruction is put in a delay slot, an undefined instruction exception does not occur. In
this case, the undefined instruction works as the NOP instruction.
46
; Branch to address pointed to by previously set RP
R8,
RP
; No effect on return operation
#1,
R0
; Update flag
Overflow
; Branch depending on execution result of above instruction
; This flag update is not referred to by above branch instruction
; Update RP and branch
RP,
R0
; Transfer RP value resulting from execution of above CALL:D
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