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CHAPTER 16 DMAC (DMA Controller)
On receiving a transfer request, DMA stores the addresses from these registers in temporary buffers
before starting the transfer.
After each transfer (access), the address counter is used to generate the next access address (based on
whether incrementing, decrementing, or constant-address is specified) and this new value is restored in
the temporary buffer. The contents of the temporary buffers are written back to the registers (DMASA
and DMADA) after transfer of each block completes.
Accordingly, the values in the address registers (DMASA and DMADA) are only updated after each
block transfer and cannot be used to determine the current transfer address in real-time.
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Number of transfers and ending transfer
Number of transfers
The transfer count register is decremented (-1) after transfer of each block completes. When the transfer
count register reaches "0" indicating that the specified number of transfers have been performed, the
DMAC indicates the termination code and halts or restarts DMA.
Like the address registers, the transfer count register is only updated after each block is transferred.
If reloading the transfer count register is disabled, transfer ends. If enabled, the register is reloaded with
its initial value and the DMAC waits for transfer to restart. (DMACB:DTCR)
The end of transfer
Transfer can be ended by the following cause. When transfer ends, cause is indicated as termination
code. (DMACB:DSS2 to DSS0)
•Specified number of transfers completed (DMACA:BLK3 to BLK0 × DMACA:DTC15 to DTC0) =>
Normal end
•Transfer halt request received from peripheral circuit => Error
•Reset occurred => Reset
A transfer halt cause code (DSS) is set for each end cause and a transfer complete interrupt or transfer
error interrupt can be generated.
386
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