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• Writing "1" to this bit is meaningless.
• When this bit is read to a read modify write instruction, 1 is always read.
• Initialized to "0" by reset.
• The read /write is possible.
[bit5] INTMn (Interrupt Mode): Interrupt mode bit
This bit can limit the PUFn bit detection at an underflow only from PRLBHn.
0
PUFn is set to 1 at an underflow.
1
PUFn is set to 1 at an underflow only from PRLBHn.
• Initialized to "0" by reset.
• The read / write is possible.
• If this bit is set to "1", an interrupt is enabled at one cycle output of PPG waveform.
• Do not rewrite this bit when the interrupt is allowed.
[bit4, bit3] PCS1/PCS0(PPG Count Select): Count clock select bits
These bits are used to select the down counter operating clock as shown below.
PCS1
PCS0
0
0
Machine clock (62.5 ns machine clock at 16 MHz)
0
1
Machine clock / 4 (250 ns machine clock at 16 MHz)
Machine clock / 16 (1 µs machine clock at 16 MHz)
1
0
Machine clock / 64 (4 µs machine clock at 16 MHz)
1
1
• Initialized to "00
" by reset.
B
• The read / write is possible.
[bit2, bit1] MD1/MD0(ppg count MoDe): Operation mode select bits
These bits are used to select the PPG timer operation mode as shown below.
MD1
MD0
0
0
8-bit PPG 2ch independent mode
0
1
8-bit prescaler + 8-bit PPG mode
1
0
16-bit PPG mode
1
1
16-bit prescaler + 16-bit PPG mode
• Initialized to "00
" by reset.
B
• The read / write is possible.
• These bits exist only in even-numbered channels.
CHAPTER 9 PPG (Programmable Pulse Generator)
Operating Mode
Operating Mode
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