Table of Contents
Advertisement
INDEX
F
fasm911
Assembler (fasm911).......................................................456
fcc911
C Compiler (fcc911) ........................................................453
Features
Features.......................................................... 2
Flag
Example of Hardware Sequence Flag Usage...................424
Hardware Sequence Flag .................................................420
I-flag...................................................................................50
Occurrence of Interrupts and Timing for Setting Flags
.........................................................................316
Flash Memory
Block Diagram of Flash Memory ....................................405
Overview of Flash Memory .............................................404
Register List of Flash Memory ........................................409
Sector Configuration of Flash Memory ...........................406
Flash Memory Status Register
Configuration of Flash Memory Status Register (FLCR)
.........................................................................410
Flash Wait Register
Configuration of the Flash Wait Register (FLWC)
.........................................................................412
FLCR
Configuration of Flash Memory Status Register(FLCR)
.........................................................................410
flnk911
Linker (flnk911)...............................................................458
FLWC
Configuration of the Flash Wait Register (FLWC)
.........................................................................412
FR-CPU Programming Mode
FR-CPU Programming Mode (16-bit,Read/write)
.........................................................................414
FR-CPU ROM Mode
FR-CPU ROM Mode (32/16/8-bit, Read Only)
.........................................................................414
Free-Run Timer
16-bit Free-Run Timer Interrupt ......................................256
16-bit Free-Run Timer Register.......................................213
Notes on Using 16-bit Free-Run Timer ...........................292
Program Example of 16-bit Free-Run Timer...................294
Free-run Timer
16-bit Output Compare and Free-run Timer Operation
.........................................................................273
A/D Activation Via Free-run Timer ................................266
Fujitsu Standard
Pins Used for Fujitsu Standard Serial Onboard Writing
.........................................................................433
G
GATE
GATE Function................................................................180
Output Status of RTO0 to RTO5 and GATE...................279
484
GATE Function Control Register
GATEC Register (GATE Function Control Register)
Gate Trigger
PPG0 Output Via Gate Trigger ....................................... 281
GATEC Register
GATEC Register (GATE Function Control Register)
,
,
,
28
48
350
H
Handling Devices
Handling Devices .............................................................. 22
Hardware
Hardware Configuration..........................................114
Initial Value of Each Hardware....................................... 180
Hardware Sequence Flag
Example of Hardware Sequence Flag Usage .................. 424
Hardware Sequence Flag................................................. 420
Harvard
Harvard
Hold Request
Hold Request Cancel Request......................................... 124
Hold Request Cancel Level
Hold Request Cancel Level Register (HRCL) ................ 119
Hold Request Cancel Register
Example of Using the Hold Request Cancel Register
HRCL
Example of Using the Hold Request Cancel Register
Hold Request Cancel Level Register (HRCL) ................ 119
I
I/O Map
I/O Map ........................................................................... 438
I/O Ports
Basic Block Diagram of I/O Ports .................................. 102
Mode for I/O Ports .......................................................... 102
ICR
ICR Bit Configuration....................................................... 51
Interrupt Control Register (ICR:ICR00 to ICR47)
ICR Mapping
ICR Mapping..................................................................... 51
ICSH
Input Capture State Control Register (ch.2, ch.3),
ICSL
Input Capture State Control Register (ch.2, ch.3),
I-flag
I-flag.................................................................................. 50
ILM
ILM Register ..................................................................... 50
......................................................................... 176
......................................................................... 176
↔
Princeton Bus Converter ............................... 30
(HRCL) ........................................................... 125
(HRCL) ........................................................... 125
......................................................................... 118
Upper Byte (ICSH23) ..................................... 237
Lower Byte (ICSL23) ..................................... 239
,
368
Advertisement
Table of Contents
