Fujitsu MB91260B Series Hardware Manual page 254

■ Input Capture State Control Register (ch.2, ch.3), Lower Byte (ICSL23)
Input capture state control register (Lower)
Bit7 Bit6
ICP3 IP2
R/W R/W
R/W: Read/Write
: Initial value
Bit5 Bit4 Bit3
ICE3 ICE2 EG31
R/W R/W R/W
EG21 EG20
0
0
1
1
EG31 EG30
0
0
1
1
ICE2
0
1
ICE3
0
1
ICP2
0
1
ICP3
0
1
CHAPTER 11 MULTIFUNCTIONAL TIMER
Bit2 Bit1 Bit0
EG30 EG21 EG20
R/W R/W R/W
Edge selection bit (input capture 2)
0 Edge is not detected (stop)
1 Rising edge is detected.
0 Falling edge is detected.
1 Both edges are detected.
Edge selection bit (input capture 3)
0 Edge is not detected (stop)
1 Rising edge is detected.
0 Falling edge is detected.
1 Both edges are detected.
Interrupt request enable bit (input capture 2)
Disable interrupt request
Enable interrupt request
Interrupt request enable bit (input capture 3)
Disable interrupt request
Enable interrupt request
Interrupt request flag bit (input capture 2)
Read
Valid edge is not detected
Valid edge is detected
Interrupt request flag bit (input capture 3)
Read
Valid edge is not detected
Valid edge is detected
ICSL23
Address: 0000B7
H
Initial value: 00000000
Write
This bit is cleared.
No effect on this bit
Write
This bit is cleared.
No effect on this bit
B
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