Fujitsu MB91260B Series Hardware Manual page 498

Delay Slot
Branch Operation with Delay Slot .................................... 45
Branch Operation without Delay Slot ............................... 47
Delayed Interrupt Control Register
DICR (Delayed Interrupt Control Register).................... 143
Delayed Register
DSP-LY (Delayed Register)............................................ 358
Delayed Write Feature
Delayed Write Feature..................................................... 360
Detection
0 Detection ...................................................................... 148
1 Detection ...................................................................... 148
Change Point Detection................................................... 149
Detection Data Register
0 Detection Data Register (BSD0) .................................. 146
1 Detection Data Register (BSD1) .................................. 146
Detection Result Register
Detection Result Register (BSRR) .................................. 147
Device States
Device States and State Transitions .................................. 93
DICR
DICR (Delayed Interrupt Control Register).................... 143
DLYI Bit of DICR........................................................... 144
Direct Addressing
Direct Addressing Area ...............................................26
DIVR
DIVR0: Base Clock Divide Ratio Setting Register 0
........................................................................... 85
DIVR1: Base Clock Divide Ratio Setting Register 1
........................................................................... 88
DLYI Bit
DLYI Bit of DICR........................................................... 144
DMA
DMA Transfer in Sleep Mode......................................... 396
Peripheral Interrupt Clear by DMA................................. 394
DMAC
DMAC Interrupt Control................................................. 396
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Control/Status Registers A
......................................................................... 371
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Control/Status Registers B
......................................................................... 375
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Overall DMAC Control
Register............................................................ 383
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Transfer Source/Transfer
Destination Address Setting Registers ............ 381
DSP-CSR
DSP-CSR (Control/Status Registers) .............................. 355
DSP-LY
DSP-LY (Delayed Register)............................................ 358
DSP-OT
DSP-OT0 to DSP-OT7 (Variable Monitor Register)
......................................................................... 358
DSP-PC
DSP-PC (Program Counter) ............................................ 357
DTCR
16-bit Dead Timer Control Register (DTCR0) ............... 245
16-bit Dead Timer Control Register (DTCR1) ............... 247
16-bit Dead Timer Control Register (DTCR2)................249
DTTI
DTTI Interrupts................................................................290
DTTI Operation of Waveform Control Register 2
(SIGCR2).........................................................290
DTTI Pin Input Operation ...............................................289
DTTI Pin Noise Cancel Feature ......................................290
E
EIRR
External Interrupt Source Register (EIRR (EIRR0,EIRR1):
External Interrupt Request Register) ...............132
EIT
EIT (Exception,Interrupt,and Trap)...................................48
EIT Sources .......................................................................48
EIT Vector Table ...............................................................53
Reception Priority of EIT Source ......................................56
Return from EIT ................................................................48
ELVR
External Interrupt Request Level Setting Register (ELVR
(ELVR0,ELVR1): External LeVel Register)
.........................................................................133
eml911
Debugger (sim911,eml911,mon911) ...............................459
ENable Interrupt Request Register
,
44
Interrupt Enable Register (ENIR (ENIR0,ENIR1): ENable
Interrupt Request Register)..............................132
End
Operation End/Stopping ..................................................395
ENIR
Interrupt Enable Register (ENIR (ENIR0,ENIR1): ENable
Interrupt Request Register)..............................132
Error Trap
Coprocessor Error Trap .....................................................61
Exception
EIT (Exception,Interrupt,and Trap)...................................48
Processing of Undefined Instruction Exception ................60
External Bus Clock
External Bus Clock Signal (CLKT)...................................74
External Count Clock
Selected External Count Clock........................................266
External Interrupt
External Interrupt Request Level.....................................135
External Interrupt Source Register (EIRR (EIRR0,EIRR1):
External Interrupt Request Register) ...............132
Operating Procedure for an External Interrupt ................134
Operation of an External Interrupt...................................134
Precautions when Returning from STOP State Using
External Interrupt.............................................137
External Interrupt Request Level Setting Register
External Interrupt Request Level Setting Register
(ELVR (ELVR0,ELVR1): External LeVel
Register)...........................................................133
External Interrupt Source Register
External Interrupt Source Register (EIRR (EIRR0,EIRR1):
External Interrupt Request Register) ...............132
INDEX
483