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CHAPTER 3 CPU AND CONTROL UNITS
If any PLL control error
oscillation stabilization wait state automatically to ensure the PLL lock time.
When the oscillation stabilization wait time has passed, the device then enters to the normal operating state.
*: Examples are an attempt to change the multiplier (multiplication factor) while the PLL is being used
and a corruption of the PLL operation enable bit.
●
Selecting the oscillation stabilization wait time
The oscillation stabilization wait time is counted by the internal timebase counter.
When an oscillation stabilization wait source occurs and the device enters the oscillation stabilization wait
state, the internal timebase counter is initialized and starts measurement of the oscillation stabilization wait
time.
The oscillation stabilization wait time setting can be selected from among four options using the OS1 and
OS0 bits (bit3 and bit2) in the STCR (standby control register).
Once selected, the oscillation stabilization wait time setting is not initialized unless the setting initialization
reset (INIT) via the external INIT pin occurs. Even when a setting initialization reset (INIT) by any other
source or an operation initialization reset (RST) occurs, the oscillation stabilization wait time set before the
occurrence of such a reset remains in effect.
The following four options are available as the oscillation stabilization wait time settings for their specific
cases:
•
OS1, OS0 = 00
Note:
For returning from the STOP mode with OSCD1 = 0 when the main PLL clock is being used as the
clock source, be sure to set the OS1 and OS0 bits in the STCR to a value other than 00
the lock wait time for the main PLL.
•
OS1, OS0 = 01
•
OS1, OS0 = 10
•
OS1, OS0 = 11
Note that the setting initialization reset (INIT) via the INIT pin must always be performed immediately
after the power is turned on.
In the conditions listed below, also, keep the low-level input to the INIT pin for the oscillation stabilization
wait time required for the oscillator circuit so that the oscillator circuit stabilizes its oscillation within that
time. (For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the
minimum value.)
•
Immediately after the power is turned on
•
In STOP mode with oscillation off
•
When main oscillation is off with the sub-clock selected as the clock source
For stable oscillation, therefore, keep the INIT pin input at "L" level for the main clock oscillation
stabilization wait time.
68
*
occurs when the PLL has been serving as the source clock, the device enters the
:No oscillation stabilization wait time
B
(The PLL oscillator stops operation with the main oscillation left working in stop
mode.)
: PLL lock wait time
B
(The oscillator does not stop operation with the external clock input or in stop
mode.)
: Oscillation stabilization wait time (Intermediate)
B
(A quickly stabilizing type of oscillator is being used, such as a ceramic resonator.)
: Oscillation stabilization wait time (Long)
B
(A general crystal oscillator is being used.)
to ensure
B
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