Fujitsu MB91260B Series Hardware Manual page 502

Output Invert Register
REVC Register (Output Invert Register) ........................ 175
Output Status
Output Status of RTO0 to RTO5 and GATE .................. 279
Output Terminal
Output Terminal Functions ............................................. 160
Overall DMAC Control Register
DMAC-ch.0,ch.1,ch.2,ch.3,ch.4 Overall DMAC Control
Register............................................................ 383
P
Package Dimension
Package Dimension ............................................................. 5
Pause-conversion Mode
Operation of Pause-conversion Mode ............................. 345
PCR
Pull-up Control Registers
(PCR:PCR0 to PCR7 and PCRG) ................... 106
PDIVR
PDIVR (Ratio of Dividing Frequency Control Register)
......................................................................... 191
PDR
Port Data Registers (PDR:PDR0 to
PDR7,PDRC,PDRD,PDRE and PDRG)
......................................................................... 104
Peripheral Clock
Peripheral Clock Signal (CLKP)....................................... 74
Peripheral Interrupt
Peripheral Interrupt Clear by DMA................................. 394
Peripheral Request
Internal Peripheral Request ............................................. 387
PFR
Port Function Registers
(PFR:PFR0 to PFR2,PFR7 and PFRG)........... 107
PICSH
PPG Output Control Register,Upper Byte (PICSH01)
......................................................................... 241
PICSL
PPG Control Register,Lower Byte (PICSL01)................ 242
Pin Assignment
Pin Assignment.................................................................... 7
Pin Description
Pin Description .................................................................... 9
PLL
Enabling/disabling PLL Operation.................................... 71
PLL Multiplier................................................................... 71
Wait Times after PLL Operation is Enabled ..................... 72
Wait Times after the PLL Multiplier is Changed.............. 72
Port Data Registers
Port Data Registers (PDR:PDR0 to PDR7, PDRC, PDRD,
PDRE and PDRG) ........................................... 104
Port Function Registers
Port Function Registers
(PFR:PFR0 to PFR2,PFR7 and PFRG)........... 107
Power
Wait Times after the Power is Turned on.......................... 72
PPG
Function of PPG ..............................................................164
PPG Combinations ..........................................................181
PPG Output Operation.....................................................178
PPG0 Output Control.......................................................281
PPG0 Output Via Gate Trigger .......................................281
PPG Activation Register
TRG Register (PPG Activation Register)........................175
PPG Control Register
PPG Control Register,Lower Byte (PICSL01)................242
PPG Output Control Register
PPG Output Control Register,Upper Byte (PICSH01)
.........................................................................241
PPGCn Register
PPGCn Register (PPGn Operation Mode Control Register)
.........................................................................172
PPGn Operation Mode Control Register
PPGCn Register (PPGn Operation Mode Control Register)
.........................................................................172
Precaution
Other Precautionary Information.....................................435
Precautions on Usage.......................................................318
Precautions when Returning from STOP State Using
External Interrupt.............................................137
Princeton
↔
Harvard Princeton Bus Converter ................................30
Priority
Reception Priority of EIT Source ......................................56
Priority Evaluation
Priority Evaluation...........................................................120
PRLL/PRLH Register
PRLL/PRLH Register (Reload Register) ........................174
Processing
Save/Restore Processing..................................................150
Program Access
Program Access .................................................................41
Program Counter
DSP-PC (Program Counter) ............................................357
Program Example
Program Example of 16-bit Free-Run Timer ..................294
Program Example of 16-bit Output Compare..................295
Programming
FR-CPU Programming Mode (16-bit,Read/write)
.........................................................................414
Programming Model
Basic Programming Model ................................................33
Protect
Enable Sector Protect.......................................................427
Sector Protect Operation List ..........................................426
Verify Sector Protect .......................................................427
Protection Function
A/D Conversion Data Protection Function......................346
Pull-up Control Registers
Pull-up Control Registers (PCR:PCR0 to PCR7 and PCRG)
.........................................................................106
INDEX
487