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■ DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Overall DMAC Control Register
[DMACR]
This register controls the overall operation of all five DMAC channels. Always use byte access to read or
write to this register.
The function of each bit is as follows.
bit
31
30
-
DMAE
bit
15
14
-
-
[bit31] DMAE (DMA Enable): DMA enabling operations
Controls operation for all DMA channels.
When DMA operation is disabled by this bit, transfer is disabled for all channels regardless of operation
state or any start/stop settings set for individual channels. Any requests on channels for which transfer is in
progress are cancelled and transfer halts at the block boundary. When disabled, any operation to start
transfer on any channel is ignored.
When DMA operation is enabled by this bit, starting and stopping each channel is available. Using this bit
to enable DMA operation does not actually start transfer for any channel.
Although writing "0" to this bit forcibly halts DMA, always use the DMAH(3:0) bits (DMACR: bit27 to
bit24) to pause DMA before forcibly halting (writing "0"). If DMA transfer is forcibly halted without
pausing, the DMA transfer halts, but the validity of the transferred data is not guaranteed. Use the DSS(2:0)
bits (DMACB: bit18 to bit16) to check whether transfer has finished.
DMAE
• Initialized to "0" when resetting.
• The read / write is possible.
[bit28] PM01 (Priority Mode ch0, 1 robin): Alternate channel priority
This setting causes the priorities for ch0 and ch1 to be alternated after each transfer.
PM01
• Initialized to "0" when resetting.
• The read / write is possible.
29
28
27
26
-
PM01
DMAH[3:0]
13
12
11
10
-
-
-
-
(Initial value: 0XX00000XXXXXXXXXXXXXXXXXXXXXXXX
0
Disables operation for all DMA channels (initial value).
1
Enables operation for all DMA channels.
0
Priority level fixed (ch0 > ch1) (initial value)
1
Priority level alternated (ch1 > ch0)
25
24
23
22
21
-
-
-
9
8
7
6
5
-
-
-
-
-
Function
Function
CHAPTER 16 DMAC (DMA Controller)
20
19
18
17
-
-
-
-
4
3
2
1
-
-
-
-
16
-
0
-
)
B
383
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