Fujitsu MB91260B Series Hardware Manual page 190

■ TRG Register (PPG Activation Register)
PPG activation register (TRG)
Address: 000130
Read/Write →
Initial value →
Read/Write →
Initial value →
[bit15 to bit0] PEN15 to PEN0 (Ppg ENable): PPG Operation Enable bits
These bits are used to select the PPG operation start and the operation mode as shown below.
PEN15 to PEN0
• Initialized to "0" by reset.
• The read / write is possible.
■ REVC Register (Output Invert Register)
Output invert register (REVC)
Address: 000134
Read/Write →
Initial value →
Read/Write →
Initial value →
[bit15 to bit0] REV15 to REV0: Output inversion bits
The PPG output values including the initial levels are inverted.
REV15 to REV0
• Initialized to "0" by reset.
• The read / write is possible.
• Since these bits invert the PPG outputs, they also invert the initial levels. The relationship between the
reload register "L" and "H" is reversed as well.
Bit15 Bit14
PEN15 PEN14
H
R/W R/W
(0) (0)
Bit7 Bit6
PEN07 PEN06
R/W R/W
(0) (0)
0
1
Bit15 Bit14
REV15 REV14
H
R/W R/W
(0) (0)
Bit7 Bit6
REV07 REV06
R/W R/W
(0) (0)
0
1
CHAPTER 9 PPG (Programmable Pulse Generator)
Bit13 Bit12 Bit11
PEN13 PEN12 PEN11
R/W R/W R/W
(0) (0) (0)
Bit5 Bit4 Bit3
PEN05 PEN04 PEN03
R/W R/W R/W
(0) (0) (0)
Operating State
Operation stop ("L" level output maintenance)
PPG enabling operations
Bit13 Bit12 Bit11
REV13 REV12 REV11 REV10
R/W R/W R/W
(0) (0) (0)
Bit5 Bit4 Bit3
REV05 REV04 REV03 REV02
R/W R/W R/W
(0) (0) (0)
Output level
Normal
Inversion
← Bit No.
Bit10 Bit9 Bit8
PEN10 PEN09 PEN08
R/W R/W R/W
(0) (0) (0)
← Bit No.
Bit2 Bit1 Bit0
PEN02 PEN01
PEN00
R/W R/W R/W
(0) (0) (0)
← Bit No.
Bit10 Bit9 Bit8
REV09 REV08
R/W R/W R/W
(0) (0) (0)
← Bit No.
Bit2 Bit1 Bit0
REV01
REV00
R/W R/W R/W
(0) (0) (0)
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