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CHAPTER 16 DMAC (DMA Controller)
16.1
Overview
This module is used to implement DMA (Direct Memory Access) transfer in FR family
devices.
This module can be used to increase system performance by using DMA transfer to
perform various types of data transfer at high speed without going via the CPU.
■ Hardware Configuration
The module consists of the following main components.
• Independent DMA channel × 5 channels
• 5 channels independent access control circuit
• 20-bit address registers (Reload specifying permitted: ch0 to ch3)
• 24-bit address registers (Reload specifying permitted: ch4)
• 16-bit transfer count registers (Reload specifying permitted: one per channel)
• 4-bit block count registers (one per channel)
• Two-cycle transfer
■ Main Function
The main data transfer functions supported by this module are as follows.
Independent data transfer can be performed for multiple channels (5 channels)
(1) Priority order (ch.0>ch.1>ch.2>ch.3>ch.4)
(2) Alternating transfer is supported between ch0 and ch1.
(3) DMAC startup factor
•Request from internal peripheral (uses interrupt requests, including the external interrupts)
•Software request (register write)
(4) Transfer mode
•Burst transfer/step transfer/block transfer
•Addressing mode with a 20-bit (24-bit) address setting (increment, decrement, fixed)
•Data types: byte, half-word, or word
•Selectable single or reload
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(Increment/decrement width of address can be ±1, 2, or 4)
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