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Table 11.4-2 Timer State Control Register, Lower Byte (TCCSL)
Bit Name
BFE:
bit7
Compare clear
buffer enabled bit
STOP:
bit6
Timer enable bit
MODE:
bit5
Timer count
mode bit
SCLR:
bit4
Timer clear bit
bit3
CLK3 to CLK0:
bit2
Clock frequency
bit1
select bit
bit0
• This bit is used to enable a compare clear buffer.
• When this bit is set to "0":
The compare clear buffer is disabled. Thus, the compare clear register (CPCLRH, CPCLRL)
can be written directly.
• When this bit is set to "1":
The compare clear buffer is enabled. The data written and stored into the compare clear
buffer is transferred to the compare clear register when the count value "0" of the 16-bit
free-run timer is detected.
• This bit is used to start/stop the 16-bit free-run timer counting.
• When this bit is set to "0": the 16-bit free-run timer counting is started.
• When this bit is set to "1": the 16-bit free-run timer counting is stopped.
Note:
When the 16-bit free-run timer stops, the operation of the output compare also stops.
• This bit is used to select a count mode of the 16-bit free-run timer.
• When this bit is set to "0":
The up count mode is selected. The timer continues to perform incremental counting until the
count value matches a compare clear register and is reset "0000
to perform incremental counting.
• When this bit is set to "1":
The up/down count mode is selected. The timer continues to perform incremental counting
until the count value matches a compare clear register. Then, the mode changes to the down
count. After that, the mode changes to the up count again when the count value reaches to
"0000
".
H
• This bit can be written even if the timer is operating or stopped. When timer is operating, the
value written to this bit is saved in a buffer. Then, the buffer value changes the count mode
when the timer value becomes "0000
• This bit is used to initialize the 16-bit free-run timer to "0000
• When this bit is set to "0": there is no meaning.
• When this bit is set to "1": the 16-bit free-run timer is initialized to "0000
• The read value is always "0".
Notes:
• When the timer count clock is the machine cycle (φ)
Writing "1" to this bit does not set the zero detection interrupt flag. The zero detection
interrupt does not occur.
• When the timer count clock is the machine cycle (φ) division
Writing "1" to this bit sets the zero detection interrupt flag. If the interrupt is enabled, the
zero detection interrupt occurs.
• These bits are used to select a count clock frequency of the 16-bit free-run timer.
• The count clock is changed immediately when these bits are set. Therefore, these bits must
be changed when the output compare and the input capture are stopped.
CHAPTER 11 MULTIFUNCTIONAL TIMER
Function
".
H
".
H
". Then, the timer restarts
H
".
H
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