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■ Count Clock Selection
The count clock to be used for this block operation uses the input for the peripheral clock and timebase
counter and can be selected from one of the following four types of count clock inputs.
The count clock operates as shown below.
PPGC0 to PPGC15 Registers
PCS1
Note that the first count cycle may become out of synchronization if the PPG side is started, in the 8-bit
prescaler + 8-bit PPG mode and the 16-bit prescaler + 16-bit PPG mode, and when the prescaler side is in
the operating state and the PPG side is in the stop state.
■ Control of Pulse Pin Output
The pulse output generated by operating this module can be outputted from external pins (PPG0 to PPG15).
In the 16-bit PPG mode, the same output can be obtained from allowing either external pin output because
PPG (m) and PPG (m + 1) output the same waveform. (m = 0, 2, 4, 6, 8, 10, 12, 14)
In the 8-bit prescaler + 8-bit PPG mode and the 16-bit prescaler + 16-bit PPG mode, the 8-bit prescaler
toggle waveform is outputted on the prescaler side, and the 8-bit PPG waveform is outputted on the PPG
side. Figure 9.4-2 shows an example of the output waveform in this mode.
PPG1
PPG0
Pl1 = T × (L1 + 1)
Ph1 = T × (L1 + 1)
Pl0 = T × (L1 + 1) × (L0 + 1)
Ph0 = T × (L1 + 1) × (H0 + 1)
Note: It is recommended to set
the same value to the PRLL
for ch1 and PRLH for ch1.
PCS0
0
0
0
1
1
0
1
1
Figure 9.4-2 Output Waveform of 8 + 8 PPG Output Operation
Ph1
Pl1
Ph0
CHAPTER 9 PPG (Programmable Pulse Generator)
Count Clock Operation
One count per peripheral clock
One count per 4 cycles of peripheral clock
One count per 16 cycles of peripheral clock
One count per 64 cycles of peripheral clock
Pl0
L1 : PRLL value for ch1 and
PRLH value for ch1
L0 : PRLL value for ch0
H0 : PRLH value for ch0
T: Input clock cycle
Ph0: High pulse width for PPG0
Pl0: Low pulse width for PPG0
Ph1: High pulse width for PPG1
Pl1: Low pulse width for PPG1
179
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