Fujitsu MB91260B Series Hardware Manual page 103

CHAPTER 3 CPU AND CONTROL UNITS
■ DIVR1: Base Clock Divide Ratio Setting Register 1
Address: 000487
Initial value (INIT)
Initial value (RST)
This register controls the frequency divide ratio for each type of internal clock signal relative to the base
clock signal.
The register sets the divide ratio for the external extended bus interface clock signal (CLKT).
If you set a combination of the source clock, main PLL multiplier, and divide ratio, which results in a
frequency higher than the maximum operating frequency, the operation of the device is not guaranteed.
Use meticulous care not to set such a combination of values. Also be careful not to select the source clock
and change settings in wrong order.
When the divide ratio setting in this register is changed, the new setting takes effect at the next clock rate.
[bit7 to bit4] T3, T2, T1, T0 (clkT divide select 3 to 0)
These bits are used to set the external bus clock (CLKT) frequency divide ratio.
The clock frequency divide ratio set by these bits applies to the clock signal (CLKT) for the external bus
interface.
The combination of values written to these bits selects the divide ratio (clock frequency) for the external
extended bus interface relative to the base clock signal, from among the 16 types listed below.
Do not set the bits to a divide ratio which results in a frequency higher than the maximum operating
frequency.
T3
0
0
0
0
0
0
0
0
...
1
(φ represents the system base clock period.)
• These bits are initialized to "0000
• A read and a write are possible.
It is advisable to set the bits to "1111
MB91260B series.
88
Bit 7
T3
H
R/W R/W
0
×
T2 T1 T0 Clock divide ratio
0 0 0
φ × 2 (Divide by 2)
0 0 1
φ × 3 (Divide by 3)
0 1 0
φ × 4 (Divide by 4)
0 1 1
φ × 5 (Divide by 5)
1 0 0
φ × 6 (Divide by 6)
1 0 1
φ × 7 (Divide by 7)
1 1 0
φ × 8 (Divide by 8)
1 1 1
... ... ...
φ × 16 (Divide by 16)
1 1 1
6 5 4
T2 T1 T0
R/W R/W R/W
0 0 0
× × ×
Clock frequency: Oscillation frequency of
φ
...
" at a reset (INIT).
B
" (divide by 16) because the external bus interface is not used by the
B
3 2 1
– – –
R/W R/W R/W
0 0 0
× × ×
4 MHz and main PLL multiplier of 8×
32 MHz (Initial value)
16 MHz
10.7 MHz
8 MHz
6.4 MHz
5.33 MHz
4.57 MHz
4 MHz
...
2 MHz
0
–
0
×