Fujitsu MB91260B Series Hardware Manual page 332

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Receive Operation in Mode 1
The ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receive transfer is
completed, and an interrupt request is generated to the CPU. The data indicating an address or data in the
9th bit becomes invalid because the receivable data length is 8 bits. The SIDR data is invalid while ORE
and FRE are active.
Figure 13.3-4 Timing for Setting ORE, FRE, and RDRF (Mode 1)
Data
ORE, FRE
RD
Receive interrupt
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Receive Operation in Mode 2
The ORE and RDRF flags are set when the last data (D7) is detected after the receive transfer is completed,
and an interrupt request is generated to the CPU. The SIDR data is invalid while ORE is active.
Figure 13.3-5 Timing of Setting ORE and RDRF (Mode 2)
Data
ORE
RDRF
Receive interrupt
D7
Address/data
D5 D6
CHAPTER 13 UART
Stop
D7
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