Registers In The Clock Generation Control Unit - Fujitsu MB91260B Series Hardware Manual

3.11.6

Registers in the Clock Generation Control Unit

This section describes the function of the registers to be used in the clock generation
control unit.
■ RSRR: Reset Source Register/watchdog Timer Control Register
Address: 000480
Initial value (INIT pin)
Initial value (INIT)
Initial value (RST)
*: Variable with the reset source
×: Not initialized
This register holds the source of the most recently generated reset, sets the time interval for the watchdog
timer, and controls its activation.
Read access to this register clears the reset source held there after it is read. If two or more resets occur
before it is read, multiple reset source flags are accumulated and set.
Write access to this register activates the watchdog timer. From then on, the watchdog timer keeps on
operating until a reset (RST) occurs.
[bit15] INIT (INITialize reset occurred)
This bit indicates whether a reset (INIT) by INIT pin input has occurred.
0
1
• The bit is initialized to "0" immediately after a read.
• A read is possible; a write does not affect the bit value.
[bit14] (reserved bit)
[bit13] WDOG (WatchDOG reset occurred)
This bit indicates whether a reset (INIT) by the watchdog timer has occurred.
0
1
• The bit is initialized to "0" immediately after either a reset (INIT) by INIT pin input or a read.
• A read is possible; a write does not affect the bit value.
[bit12] (reserved bit)
Bit 15
INIT
H
R
1
*
×
INIT by INIT pin input has not occurred.
INIT by INIT pin input has occurred.
INIT by watchdog timer has not occurred.
INIT by watchdog timer has occurred.
CHAPTER 3 CPU AND CONTROL UNITS
14 13 12
– WDOG – SRST
R R R
0 0 0
* * ×
× × *
11 10 9
– WT1 WT0
R R R/W R/W
0 0 0
× * 0
* × 0
8
0
0
0
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