Fujitsu MB91260B Series Hardware Manual page 394

[bit18 to bit16] DSS2 to DSS0 (Dma Stop Status)*: Transfer halt cause indication
This 3-bit code (termination code) indicates the reason why DMA transfer stopped or halted on the
corresponding channel. The termination code meanings are as follows.
DSS2
DSS1, DSS0
00
01
10
11
The transfer stop request is only be set when a request from a peripheral circuit is used.
Note:
The "Interrupt generation" column indicates the type of interrupt request that could be generated.
• Initialized to "000B" when resetting.
• Writing "000B" clears the bits.
• Although both reading and writing are permitted, only "000
[bit15 to bit8] SASZ7 to SASZ0 (Source Addr count SiZe) *: Count size specification for the
Specifies how much to increment or decrement the transfer source address (DMASA) for the corresponding
channel after each transfer. The value specified by these bits determines by how much the address is
incremented or decremented for each transfer. Whether to increment or decrement the address is specified
by the transfer source address count mode (SADM).
• Initialized to "00000000
• The read / write is possible.
• If setting other than a fixed address, ensure that the setting matches the transfer data size (WS).
0 Initial value
1 DMA is suspended (DMAH, PAUS bit, interrupt, etc.).
Normal completion
SASZ
00
H
01
H
02
H
04
H
Other than above
" when resetting.
B
CHAPTER 16 DMAC (DMA Controller)
Function
Function
Initial value
-
Transfer halt request
" is meaningful when writing.
B
Address fixed
Transfer by byte unit
Transfer by half-word unit
Transfer by word unit
Setting disabled
Interrupt generation
None
None
Interrupt generation
None
None
Error
End
transfer source address
Function
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