Fujitsu MB91260B Series Hardware Manual page 368

Table 15.1-1 Block Diagram Outline Explanation
Block Register
Operation control DSP-CSR
DSP-PC
I-RAM
Instruction control
IF
DEC1*
DEC*
X-RAM
Y-RAM
Arithmetic unit
MUL*
ADD*
ACC*
CLP*
RND*
SLQ*
DSP-LY
Delayed register
LY-DLY*
DSP-OT0
Variable monitor
to
output
DSP-OT7
*: Access from CPU disabled.
CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR
Operation control register of multiplication and addition calculation macro
The following operations are controlled from the CPU and servo block.
• Calculation start/end instructions
• Interrupt control
• Program flow control (used for conditional branching commands of
multiplication and addition macro)
Program counter
Program execution begins from the first address specified by the CPU.
Instruction RAM of 256 × 16-bit
The CPU can perform R/W while the multiplication and addition macro
calculation is halted.
Load the command code from the CPU before starting calculations.
Instruction fetch register
Instruction decoder
Data RAM of 64 × 16-bit
The CPU can perform R/W while the multiplication and addition macro
calculation is halted.
Load the coefficient from the CPU before starting calculations.
Data RAM of 64 × 16-bit
The CPU can perform R/W while the multiplication and addition macro
calculation is halted.
Load the variable from the CPU before starting calculations.
16 x 16 → 32-bit multiplier
32 + 40 → 40-bit adder
40-bit accumulator
When sending from 40 to 16 bits, if there is out-of-range 16-bit data, saturated
to the maximum value.
When sending from 40 to 16 bits, the lower-order bits are rounded.
When sending from 40 to 16 bits, select the bits to send.
Delayed register
During multiplication and addition, you can save the variable value, and write
it back to Y-RAM.
Variable monitor output register
Stores the same value as addresses 0 to 7 of Y-RAM.
During calculation (when Y-RAM access is disabled), you can monitor
addresses 0 to 7 of Y-RAM.
Function
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