Fujitsu MB91260B Series Hardware Manual page 243

CHAPTER 11 MULTIFUNCTIONAL TIMER
■ Output Compare Register
(OCCPH: OCCPH0 to OCCPH5, OCCPL: OCCPL0 to OCCPL5)
Output compare register (Upper)
OCCPH0 to OCCPH5
Address:
000090
H
000092
H
000094
H
000096
H
000098
H
00009A
H
Output compare register (Lower)
OCCPL0 to OCCPL5
The output compare register is a 16-bit register used to compare with the count value of the 16-bit free-run
timer. Set the value of the output compare buffer register (OCCPBH, OCCPBL) before the timer operation
is enabled.
When the value of the output compare register matches the count value of the 16-bit free-run timer, a
compare signal is generated and the output compare interrupt flag bit (the lower of the compare control
register (OCSL0, OCSL2 OCSL4), IOP1, IOP0: bit7, bit6) is set. When the output level is set (the upper of
the compare control register (OCSH1, OCSH3, OCSH5), OTD1, OTD0: bit9, bit8), an output level waveform
generator (RTO0 to RTO5) corresponding to the output compare register (OCCPH0 to OCCPH5, OCCPL0
to OCCPL5) can be reversed.
To access this register, use a halfword or word access instruction.
228
Bit15 Bit14
OP15 OP14
Read →
R R
Initial value →
(0) (0)
Bit7 Bit6
OP07 OP06
R R
Read
Initial value →
(0) (0)
Bit13 Bit12 Bit11
OP13 OP12 OP11
R R R
(0) (0) (0)
Bit5 Bit4 Bit3
OP05 OP04 OP03
R R R
(0) (0) (0)
Bit10 Bit9 Bit8
OP10 OP09 OP08
R R R
(0) (0) (0)
Bit2 Bit1 Bit0
OP02 OP01 OP00
R R R
(0) (0) (0)