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CHAPTER 11 MULTIFUNCTIONAL TIMER
*1: It is necessary to activate PPG 0 beforehand.
*2: In order to generate a non-overlapping signal, first select 2-channel mode (compare control register
higher-order (OCSH1, OCSH3, and OCSH5) CMOD: bit12 = 1) for RT1, RT3, and RT5.
*3: The GATE signal is generated from the RTx whose GTENx bit is set to "1".
*4: The GATE signal is generated while the timer activated by the RTx whose GTENx bit is set to "1" is
operating. If more than one GATEx bit is set to "1", the GATE signal is the OR of the signals for each
of the operating timers.
Note:
RTO0 and RTO1 are controlled by the 16-bit dead timer control register's higher order (DTCR0)
TMD2 to TMD0: bit10 to bit8; RTO2 and RTO3 are controlled by lower-order register's (DTCR1)
TMD5 to TMD3: bit2 to bit0; and RTO4 and RTO5 are controlled by the higher-order register's
(DTCR2) TMD8 to TMD6: bit10 to bit8.
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