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CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
[bit10] OVIE: Counter overflow interrupt request enable bit
This bit controls a counter overflow interrupt request as described below.
0
1
• Initialized to "0" when resetting.
• The read / write is possible.
[bit9] ERR: Error flag
The flag indicates that the next measuring is completed before reading the measurement result in PWCR0
or PWCR1 in the continuous measurement mode of the pulse width count mode. At this point, the PWCR0
or PWCR1is updated to a new measurement result, the previous measurement result will be lost. The
measurement is continued regardless of this bit value.
Set factor
Clear factor
• Initialized to "0" at resetting.
• This bit is read-only. Writing does not change the bit value.
[bit8] (Reserved)
Reserved bit.
Read value is "0".
Be sure to write "0".
[bit7, bit6] CKS1, CKS0: Clock selection bits
Select an internal counter as listed in the table below.
CKS1
0
0
1
1
• Initialized to "00
• The read / write is possible. Do not set "11
• These bits must not be updated after starting. These bits must be written before starting or after stopped.
188
Disable the overflow interrupt request output (an interrupt not generated when OVIR is set)
[Initial value]
Enable overflow interrupt request output (interrupt is generated when OVIR is set)
Set when the measurement result has not been read is lost because of the next result.
Cleared when PWCR0 or PWCR1 (measurement result) is read.
CKS0
0
Clock generated by dividing the machine clock by 4 [Initial value]
1
Clock generated by dividing the machine clock by 16
0
Clock generated by dividing the machine clock by 32
1
Setting disabled
" at resetting.
B
Count Clock Selection
".
B
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