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[Circuits which stop in the sleep state]
CPU during program execution
The following circuits work when DMA transfer occurs:
• Bit search module
• Built-in memory modules
• Internal/external buses
However, the MB91260B series does not support the external bus mode.
[Circuits which do not stop in the sleep state]
• Oscillator circuit
• Operation-enabled main PLL
• Clock generation control unit
• Interrupt controller
• Peripheral circuits
• Watch timer
• Main oscillation stabilization wait timer
• DMA controller
• On chip Debug Support Unit (DSU)
[Sleep-state return sources]
•
Occurrence of a valid interrupt request
When a request for an interrupt not disabled (1111
canceled and the device enters the RUN state (normal operating state). In this case, set the I-flag in the
PS register of the CPU to "1" to enable interrupts and execute the interrupt handler after returning from
the sleep state.
The sleep mode is not canceled even when a request for an interrupt disabled (1111
register occurs.
•
Occurrence of a setting initialization reset (INIT) request
When a setting initialization reset (INIT) request occurs, the device enters the setting initialization reset
(INIT) state unconditionally.
•
Occurrence of an operation initialization reset (RST) request
When an operation initialization reset (RST) request occurs, the device enters the operation
initialization reset (RST) state unconditionally.
For the priority of each type of source, see "● Priorities of state transition requests" of the section 3.12
"Device Status Control".
[Synchronous standby operation]
When the SYNCS bit (bit8) in the TBCR (timebase counter control register) contains "1", the synchronous
standby operation is enabled. In this case, the device does not enter the sleep state only by writing to the
SLEEP bit. It enters the sleep state by reading the STCR register after that.
To enter the sleep mode, be sure to use the sequence given in [Transition to sleep mode].
●
Stop mode
Writing "1" to the STOP bit (bit7) in the STCR (standby control register) establishes the stop mode,
causing the transition to the stop state. The device remains in the stop state until a stop-state return source
(an event that triggers the device to return from the stop state) is generated.
CHAPTER 3 CPU AND CONTROL UNITS
) in the ICR register occurs, the sleep mode is
B
) in the ICR
B
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