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BUS OVERVIEW
3.4.2.
Arbitration Phase Signals
This signal group is used to arbitrate for the bus.
Pin/Signal Name
Symmetric Agent Bus Request
Priority Agent Bus Request
Block Next Request
Lock
Up to five agents can simultaneously arbitrate for the bus, one to four symmetric agents (on
BREQ[3:0]#) and one priority agent (on BPRI#). Pentium Pro processors arbitrate as symmetric
agents. The priority agent normally arbitrates on behalf of the I/O subsystem (I/O agents) and
memory subsystem (memory agents).
Owning the bus is a necessary condition for initiating a bus transaction.
The symmetric agents arbitrate for the bus based on a round-robin rotating priority scheme. The
arbitration is fair and symmetric. After reset, agent 0 has the highest priority followed by agents
1, 2, and 3. All bus agents track the current bus owner. A symmetric agent requests the bus by
asserting its BREQn# signal. Based on the values sampled on BREQ[3:0]#, and the last sym-
metric bus owner, all agents simultaneously determine the next symmetric bus owner.
The priority agent asks for the bus by asserting BPRI#. The assertion of BPRI# temporarily
overrides, but does not otherwise alter the symmetric arbitration scheme. When BPRI# is sam-
pled active, no symmetric agent issues another unlocked bus transaction until BPRI# is sampled
inactive. The priority agent is always the next bus owner.
BNR# can be asserted by any bus agent to block further transactions from being issued to the
bus. It is typically asserted when system resources (such as address and/or data buffers) are
about to become temporarily busy or filled and cannot accommodate another transaction. After
bus initialization, BNR# can be asserted to delay the first bus transaction until all bus agents are
initialized.
The assertion of the LOCK# signal indicates that the bus agent is executing an atomic sequence
of bus transactions that must not be interrupted. A locked operation cannot be interrupted by an-
other transaction regardless of the assertion of BREQ[3:0]# or BPRI#. LOCK# can be used to
implement memory-based semaphores. LOCK# is asserted from the first transaction's Request
Phase through the last transaction's Response Phase.
3-12
Table 3-3. Arbitration Phase Signals
Pin Mnemonic
BR[3:0]#
BPRI#
BNR#
LOCK#
Signal Mnemonic
Number
BREQ[3:0]#
BPRI#
BNR#
LOCK#
4
1
1
1
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