Xapp661: Rocketio Transceiver Bit-Error Rate Tester; Xapp662: In-Circuit Partial Reconfiguration Of Rocketio Attributes; Rocketio Transceivers - Xilinx RocketIO User Manual

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Application Notes
in this document uses the PPC405 core device control register (DCR) bus interface to
implement a simple solution with a minimum of FPGA resources.

XAPP661: RocketIO Transceiver Bit-Error Rate Tester

This application note describes the implementation of a RocketIO transceiver bit-error rate
tester (BERT) reference design demonstrating a serial link (1.0 Gb/s to 3.125 Gb/s)
between two RocketIO multi-gigabit transceivers (MGT) embedded in a single
Virtex-II Pro FPGA. To build a system, an IBM CoreConnect™ infrastructure connects the
PowerPC™405 processor (PPC405) to external memory and other peripherals using the
processor local bus (PLB) and device control register (DCR) buses. The reference design
uses a two-channel Xilinx bit-error rate tester (XBERT) module for generating and
verifying high-speed serial data transmitted and received by the RocketIO transceivers.
The data to be transmitted is constructed using pseudorandom bit sequence (PRBS)
patterns. The receiver in XBERT module compares the incoming data with the expected
data to analyze for errors. The XBERT supports several different types of user selectable
PRBS patterns. Frame counters in the receiver are used to track the total number of data
words (frames) received, and total number of data words with bit errors. The processor
reads the status and counter values from the XBERT through the PLB Interface, then sends
out the information to the UART.

XAPP662: In-Circuit Partial Reconfiguration of RocketIO Attributes

This application note describes in-circuit partial reconfiguration of RocketIO transceiver
attributes using the Virtex-II Pro internal configuration access port (ICAP). The solution
uses a Virtex-II Pro device with an IBM PowerPC™ 405 (PPC405) processor to perform a
partial reconfiguration of the RocketIO multi-gigabit transceivers (MGTs) pre-emphasis
and differential swing control attributes. These attributes must be modified to optimize the
MGT signal transmission prior to and after a system has been deployed in the field. This
solution is also ideal for characterization, calibration, and system testing.
The hardware and software elements of this solution can be easily integrated into any
Virtex-II Pro design already utilizing the PLB or OPB bus structures. The reference design
uses a Xilinx intellectual property interface (IPIF) connecting to either the PLB or OPB
buses. This design also provides for a terminal interface using a serial port connection,
allowing MGT attribute settings to be changed through command line entries. Design
modules are also included to facilitate bit-error rate tests (BERT) and pseudo-random
binary sequence (PRBS) diagnostics.
XAPP669: PPC405 PPE Reference System Using Virtex-II Pro

RocketIO Transceivers

The PPC405 Packet Processing Engine (PPE) Reference System using Virtex-II Pro™
RocketIO™ transceivers addresses the need in the digital communications market for high
speed data transfer. Serial protocols can be controlled by complex logic, but are more
simply handled by a microprocessor—in this case, the IBM® PowerPC® 405 (PPC405)
processors embedded in the Virtex-II Pro™ FPGA. This reference system is an example of
a high-speed serial-link packet processing engine implemented in Virtex-II Pro FPGAs.
The Embedded Development Kit (EDK) is used exclusively in the design and
implementation of both hardware and software in this reference system. This reference
design has been verified on the Memec Design Virtex-II Pro P4 Development Board.
Instructions are included to allow the reader to reproduce the design on this board.
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
www.xilinx.com
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