Revision History - Xilinx Virtex-7 FPGA VC7203 Getting Started Manual

Revision History

The following table shows the revision history for this document.
Date Version
11/07/2012 1.0
01/23/2013 2.0
07/10/2013 3.0
11/06/2013 4.0
12/18/2013 5.0
04/16/2014 6.0
06/12/2014 7.0
10/08/2014 8.0
11/24/2014 9.0
04/27/2015 2015.1
VC7203 IBERT Getting Started Guide
UG847 (Vivado Design Suite v2015.1) April 27, 2015
Initial Xilinx release.
Updated for ISE® Design Suite 14.4 and Vivado® Design Suite 2012.4.
Updated for Vivado® Design Suite 2013.2. Updated
Launching the Vivado Design Suite Software, page 14,
Module, and Creating the GTX IBERT Core
Updated for Vivado Design Suite 2013.3. Device number was corrected from
XC7V485T to XC7VX485T. Updated most figures in
Started Guide. The ZIP project file name changed to
rdf0272-vc7203-ibert-2013-3.zip. In
changed to Xilinx TCF agent.
Figure 1-31, Synthesize Out-Of-Context Module was deleted. Updated
Additional Resources and Legal Notices
Updated for Vivado Design Suite 2013.4. Updated
Figure 1-17, Figure 1-19,
Updated for Vivado Design Suite 2014.1. File lists changed under
Project Files. The ZIP project file name changed to
rdf0272-vc7203-ibert-2014-1.zip. The Demonstration Design of the last row
of Table 1-1 changed to led_scroll.bit. Launching the Vivado Design Suite
Software was changed to
Starting the SuperClock-2 Module
changed to Add Link. The section
figures from Figure 1-10
Manager Window, and Figure
Updated for Vivado Design Suite 2014.2. Updated
Figure 1-15, Figure 1-17,
Figure 1-33, and Figure 1-35. Updated
Updated for Vivado Design Suite 2014.3. The ZIP project file name changed to
rdf0272-vc7203-ibert-2014-3.zip. Updated
Figure 1-10, Figure 1-11,
Figure 1-33, and Figure 1-34. The demonstration design in the last row of
changed to LED Scroll. C_USER_SCAN_CHAIN* changed from 2 to 3 in
path for the bitstream changed in
Updated for Vivado Design Suite 2014.4. The ZIP project file name changed to
rdf0272-vc7203-ibert-2014-4.zip. Updated
Module. Updated Figure
Updated for Vivado Design Suite 2015.1. The ZIP project file name changed to
rdf0272-vc7203-ibert-2015-1.zip. The connector in
Updated Figure 1-4, Figure
and Figure 1-27. Version changed to match the software release.
www.xilinx.com
Revision
for the latest procedures.
Figure
Figure 1-30 was renamed Design Sources File Hierarchy.
links.
Figure 1-20, Figure 1-23, and
Setting Up the Vivado Design
was updated. In
In Case of RX Bit Errors
through Figure 1-35, including adding
1-35, Bitstream Generation Completed.
Figure 1-19, Figure 1-20,
Viewing GTX Transceiver
Figure 1-19, Figure 1-21
step 19, page 39.
1-23.
1-10, Figure 1-15, Figure
Extracting the Project Files,
Starting the SuperClock-2
Chapter 1, VC7203 IBERT Getting
1-11, Digilent JTAG cable
Appendix A,
Figure 1-10 through Figure
Figure 1-27.
Extracting the
Suite. The procedure in
step 6, page 21, Add (+) was
was added. Updated 19
Figure 1-31, Project
Figure 1-10 through Figure
Figure 1-23, Figure 1-27,
Operation.
In Case of RX Bit Errors. Updated
through Figure 1-27, Figure
Table 1-1
Figure 1-33. The
Starting the SuperClock-2
Figure 1-4 was updated.
1-18, Figure 1-20, Figure
1-15,
1-12,
1-29,
1-23,
2