Power Management - Xilinx ZC706 User Manual

Table 1-35: XADC Measurements through MUX U6 (Cont'd)
Meas. Current
Rail Name
Type Range
V VADJ_FPGA
I VADJ_FPGA CS 0A-2A
V VCC3V3_FPGA
I VCC3V3_FPGA CS 0A-2A

Power Management

[Figure 1-2, callout 32]
The ZC706 board uses power regulators and a PMBus-compliant system controller from
Texas Instruments to supply core and auxiliary voltages. The Texas Instruments Fusion
Digital Power graphical user interface is used to monitor the voltage and current levels of
the board power modules.
The PCB layout and power system design meet the recommended criteria described in
Zynq-7000 All Programmable SoC PCB Design and Pin Planning Guide (UG933).
The ZC706 evaluation board power distribution diagram is shown in
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
Isense Op Amp
Reference
Gain
Designator
NA VADJ_FPGA 2.5V REMOTE SENSE
DIVIDED TO DELIVER 0.625V ON
VADJ_FPGA_XADC_P
U70 100
NA VCC3V3_FPGA REMOTE SENSE
DIVIDED TO DELIVER 0.825V ON
VCC3V3_FPGA_XADC_P
U97 100
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Schematic Net Name
Vo Range
VADJ_FPGA_XADC_P
VADJ_FPGA_SENSE_N
0V-1V VADJ_FPGA_XADC_CS_P
VADJ_FPGA_XADC_CS_N
VCC3V3_FPGA_XADC_P
VCC3V3_FPGA_SENSE_N
0V-1V VCC3V3_FPGA_XADC_CS_P
VCC3V3_FPGA_XADC_CS_N
Feature Descriptions
8-to-1 MUX U6
MUX A[2:0]
Pin Pin
Num Name
23 S5A 100
7 S5B
24 S6A 101
6 S6B
25 S7A 110
5 S7B
26 S8A 111
4 S8B
Figure 1-35.
77
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