Xilinx ZC702 User Manual
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Xilinx ZC702 User Manual

For the zynq-7000 xc7z020 soc
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ZC702 Evaluation Board
for the Zynq-7000
XC7Z020 SoC
User Guide
UG850 (v1.7) March 27, 2019

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Summary of Contents for Xilinx ZC702

  • Page 1 ZC702 Evaluation Board for the Zynq-7000 XC7Z020 SoC User Guide UG850 (v1.7) March 27, 2019...

  • Page 2: Please Read: Important Legal Notices

    Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...
  • Page 3 GND changed to GA0 = 0 = GND in Table 1-28 Table 1-29. The Appendix C Master UCF Listing was replaced with the Xilinx Design Constraints (XDC) file listing. The link in Declaration of Conformity was updated. 04/30/2015 Description added to FMC Connector JTAG Bypass.
  • Page 4 Xilinx Design Constraints, the constraints file list is removed, and access instructions are added. Updated Appendix E, Regulatory and Compliance Information. Corrected the v1.6.1 revision history date to 06/29/2018. ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 5: Table Of Contents

    Revision History ..............2 Chapter 1: ZC702 Evaluation Board Features Overview .
  • Page 6 Appendix B: VITA 57.1 FMC Connector Pinouts Appendix C: Xilinx Design Constraints Overview ............... 72 Appendix D: Board Specifications Dimensions .
  • Page 7 Xilinx Resources ........

  • Page 8: Chapter 1: Zc702 Evaluation Board Features

    Other features can be supported using VITA-57 FPGA mezzanine cards (FMC) attached to either of two low pin count (LPC) FMC connectors. ZC702 Board Features The ZC702 board features are listed in here. Detailed information for each feature is provided in Feature Descriptions.
  • Page 9 Power on/off slide switch • Power management with PMBus voltage and current monitoring via TI power controllers • Dual 12-bit 1 MSPS XADC analog-to-digital front end • Configuration options: ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 10: Block Diagram

    Platform cable header JTAG configuration port ° 20-pin PL PJTAG header ° 20-pin PS JTAG header ° Block Diagram The ZC702 board block diagram is shown in Figure 1-1. X-Ref Target - Figure 1-1 Quad SPI JTAG Module DDR3 Memory...

  • Page 11: Board Layout

    Put the adapter down only on an antistatic surface such as the bag supplied in your kit. • If you are returning the adapter to Xilinx Product Support, place it back in its antistatic bag immediately. ZC702 Board User Guide www.xilinx.com...
  • Page 12 Round callout references a component Square callout references a component on the front side of the board on the back side of the board UG850_c1_02_032013 Figure 1-2: ZC702 Board Component Locations Table 1-1: ZC702 Board Component Descriptions Schematic Reference Callout...
  • Page 13 Electrostatic Discharge Caution Table 1-1: ZC702 Board Component Descriptions (Cont’d) Schematic Reference Callout Component Description Notes 0381449 Page Designator Number Molex 67840-8001 SDIO Memory card SD Card Interface connector connector Programmable Logic JTAG Programming Options with integrated Digilent USB JTAG Module...

  • Page 14: Feature Descriptions

    Zynq-7000 XC7Z020 SoC [Figure 1-2, callout 1] The ZC702 board is populated with the Zynq-7000 XC7Z020-1CLG484C SoC. The XC7Z020 SoC consists of an SoC-style integrated processing system (PS) and programmable logic (PL) on a single die. The high-level block diagram is shown in Figure 1-3.
  • Page 15 For additional information on Zynq-7000 SoC devices, see the Zynq-7000 SoC Data Sheet: Overview (DS190) [Ref 1] and the Zynq-7000 SoC Technical Reference Manual (UG585) [Ref 2] for more information about Zynq-7000 SoC configuration options. ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 16: Device Configuration

    PL must be powered on to enable the use of the security block located within the PL, which provides 256-bit AES and SHA decryption/authentication. The ZC702 board supports these configuration options: • PS Configuration: Quad SPI flash memory •...

  • Page 17: Encryption Key Backup Circuit

    Feature Descriptions Encryption Key Backup Circuit The XC7Z020 SoC U1 implements bitstream encryption key technology. The ZC702 board provides the encryption key backup battery circuit shown in Figure 1-5. X-Ref Target - Figure 1-5 VCCAUX 200 mW BAS40-04 4.70K 1% To SoC 1/16Ω...

  • Page 18: I/O Voltage Rails

    Datapath width: 32 bits • Data rate: Up to 1,333 MT/s The ZC702 XC7Z020 SoC PS DDR bank 502 interface performance is documented in the Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020): DC and AC Switching Characteristics (DS187) data sheet [Ref The DDR3 0.75V V...
  • Page 19 DQ18 PS_DDR3_DQ19 DQ19 PS_DDR3_DQ20 DQ20 PS_DDR3_DQ21 DQ21 PS_DDR3_DQ22 DQ22 PS_DDR3_DQ23 DQ23 PS_DDR3_DQ24 DQ24 PS_DDR3_DQ25 DQ25 PS_DDR3_DQ26 DQ26 PS_DDR3_DQ27 DQ27 PS_DDR3_DQ28 DQ28 PS_DDR3_DQ29 DQ29 PS_DDR3_DQ30 DQ30 PS_DDR3_DQ31 DQ31 PS_DDR3_DM0 ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...
  • Page 20 U66, U67, U68, U69 PS_DDR3_BA2 U66, U67, U68, U69 PS_DDR3_CLK_P U66, U67, U68, U69 PS_DDR3_CLK_N CK_B U66, U67, U68, U69 PS_DDR3_CKE U66, U67, U68, U69 PS_DDR3_WE_B WE_B U66, U67, U68, U69 ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 21: Quad-Spi Flash Memory

    U66, U67, U68, U69 PS_VRN PS_VRP VTTVREF_PS VTTVREF_PS The ZC702 DDR3 4x 8-bit component memory interface adheres to the constraints guidelines Note: documented in the DDR3 Design Guidelines section of the 7 Series FPGAs Memory Interface Solutions v1.8 User Guide (UG586) [Ref 4].

  • Page 22: Usb 2.0 Ulpi Transceiver

    [Ref 2] provides details on using the Quad-SPI flash memory. Figure 1-6 shows the connections of the linear Quad SPI flash memory on the ZC702 board. For more details, see the Micron N25Q128A11ESF40G data sheet at the Micron website [Ref 14].
  • Page 23 USB Connector USB3320 (U9) Net Name Description Name VBUS USB_VBUS_SEL +5V from host system USB_D_N Bidirectional differential serial data (N-side) USB_D_P Bidirectional differential serial data (P-side) Signal ground ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...
  • Page 24 Mini-B connector (J1) can be tied to GND by a jumper on header J36 pins 1–2 (default). The USB shield can optionally be connected through a capacitor to GND by installing a capacitor (body size 0402) at location C202 and jumping pins 2-3 on header J36. ZC702 Board User Guide www.xilinx.com Send Feedback...
  • Page 25 2-3 = HOST OR OTG MODE VCC3V3 R280 USB HOST POWER 1/10Ω MIC2025_SOP8 VCC5V0 OUT2 OUT1 C293 LED-RED-SMT 0.1μF 150μF SOP127P500X600_8 TANT UG850_c1_07_032719 Figure 1-7: USB 2.0 ULPI Transceiver ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 26: Sd Card Interface

    [Figure 1-2, callout 5] The ZC702 board includes a secure digital input/output (SDIO) interface to provide user-logic access to general purpose nonvolatile SDIO memory cards and peripherals. Information for the SD I/O card specification can be found at the SanDisk Corporation...

  • Page 27: Programmable Logic Jtag Programming Options

    PS_MIO44 SDIO_DAT0_LS DAT0 PS_MIO43 SDIO_CD_DAT3_LS CD_DAT3 Programmable Logic JTAG Programming Options [Figure 1-2, callout 6] The ZC702 board JTAG chain is shown in Figure 1-9. X-Ref Target - Figure 1-9 SPST Bus Switch SPST Bus Switch JTAG Header N.C. N.C.

  • Page 28: Programmable Logic Jtag Select Switch, Jtag Cable Connector

    Digilent bridge DIGILENT_TCK TS5A3359 SP3T JTAG_TDI ANALOG SWITCH 20PIN_JTAG_TDI JTAG_TMS To J58 20PIN_JTAG_TMS Parallel Cable JTAG_TCK (20 Pins) 20PIN_JTAG_TCK UG850_c1_10_032719 Figure 1-10: PL JTAG Programming Source Analog Switch ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 29: Fmc Connector Jtag Bypass

    TDI-to-TDO connection using a device or bypass jumper to ensure that the JTAG chain connects to the XC7Z020 SoC. Clock Generation The ZC702 board provides three clock sources for the XC7Z020 SoC. Table 1-11 lists the source devices for each clock.

  • Page 30: System Clock

    Figure 1-11. X-Ref Target - Figure 1-11 VCC2V5 SIT9102 200 MHz Oscillator 0.1 μF 10V SYSCLK_N R168 OUT_B 100Ω 1% SYSCLK_P UG850_c1_11_030513 Figure 1-11: System Clock Source ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 31: Programmable User Clock

    156.250 MHz. User applications can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the ZC702 board reverts the user clock to the default frequency of 156.250 MHz. •...

  • Page 32: 10/100/1000 Mhz Tri-Speed Ethernet Phy

    [Figure 1-2, callout 9] The ZC702 board uses the Marvell Alaska PHY device (88E1116R) at U35 for Ethernet communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports RGMII mode only. The PHY connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector (P2) with built-in magnetics.

  • Page 33: Ethernet Phy Clock Source

    X-Ref Target - Figure 1-14 C322 18pF 50V 25.00 MHz PHY XTAL OUT R246 C333 PHY XTAL IN 18pF 50V UG850_c1_14_030513 Figure 1-14: Ethernet PHY Clock Source ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 34: Usb-To-Uart Bridge

    USB port. The USB cable is supplied in the ZC702 Evaluation Kit (Standard-A end to host computer, Type Mini-B end to ZC702 board connector J17). The CP2103GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into the USB port on the ZC702 board.

  • Page 35: Hdmi Video Output

    [Figure 1-2, callout 13] The ZC702 board provides a high-definition multimedia interface (HDMI®) video output using an Analog Devices ADV7511KSTZ-P HDMI transmitter at U40. The HDMI output is provided on a Molex 500254-1927 HDMI type-A receptacle at P1. The ADV7511 supports 1080P 60Hz, YCbCr 4:2:2 encoding via 16-bit input data mapping.
  • Page 36 DSD5 DSD_CLK MCLK GND1 GND2 GND3 I2S0 GND4 I2S1 GND5 I2S2 GND6 I2S3 GND7 SCLK GND8 LRCLK GND9 GND10 R_EXT GND11 R107 UG850_c1_15_032719 Figure 1-15: HDMI Codec Circuit ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...
  • Page 37 HDMI receptacle P1. Table 1-18: ADV7511 to HDMI Receptacle Connections ADV7511 (U40) Net Name HDMI Receptacle P1 Pin HDMI_D0_P HDMI_D0_N HDMI_D1_P HDMI_D1_N HDMI_D2_P ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 38: I2C Bus

    [Figure 1-2, callout 14] The ZC702 board implements a single I2C port on the XC7Z020 SoC (IIC_SDA_MAIN, IIC_SDA_SCL), which is routed through an TI Semiconductor PCA9548 1-to-8 channel I2C bus switch (U44). The bus switch can operate at speeds up to 400 kHz.

  • Page 39: Real-Time Clock

    Clock counter, alarm and fixed-cycle timer interrupt functions Programming information for the RTC-8564JE is available in the RTC-8564JE/NB Application Manual at the Epson Electronics America website [Ref 22]. ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 40: I/O Expansion Header

    The 2 x 6 I/O expansion header J54 supports Digilent Pmod Peripheral Modules. 8 pins (IIC_PMOD[0:7]) are connected to the TI TCA6416APWR I2C expansion port device U80. See the Digilent website for information on Digilent Pmod Peripheral Modules [Ref 23]. ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 41: High Speed Can Transceiver

    The TJA1040 (U14) is an advanced high speed Controller Area Network (CAN) transceiver for use in automotive and general industrial applications. It supports the differential bus signal representation described in the international standard for in-vehicle high speed CAN applications (ISO 11898). ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...
  • Page 42 Table 1-21: CAN Transceiver SoC Connections TJA1040 (U14) TXS0104E Level Shifter (U3) XC7Z020 SoC (U1) Net Name Net Name Low Side Net Bank CAN_TXD CAN_TXD_LS PS_MIO47 CAN_RXD CAN_RXD_LS PS_MIO46 CAN_STB_B CAN_STB_B_LS PS_MIO9 ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 43: Status Leds

    Green Power ON UCD9248 Power Controllers U32, U33, U34 DS13 PWRCTL_PWRGOOD Green Power Good (board supply voltages minimum > operating voltage) DS24 PWRCTL1_VCC4A_PG Green FMC1, FMC2 Power Good ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 44: Ethernet Phy User Leds

    UG850_c1_20_032719 Figure 1-20: Ethernet PHY User LEDs User I/O [Figure 1-2, callout 17–28] The ZC702 board provides the following user and general purpose I/O capabilities: • Ten user LEDs (callout 17) PMOD0 0–PMOD0 3 and PMOD1 0–PMOD1 3: DS15–DS22 °...

  • Page 45: User Leds

    [Figure 1-2, callout 17] The ZC702 board supports eight user LEDs connected to XC7Z020 SoC Banks 13, 33, 34, and 35 through level-shifters. Note that the LEDs are wired in parallel with headers J63 (PMOD1) and J62 (PMOD2). These headers are described in User PMOD GPIO Headers.
  • Page 46 460 mW 460 mW VCC3V3 VCC3V3 DS23 DS12 VCCMIO (1.8V) R416 R393 20.5K 0.1Ω 0.1W 0.1Ω NDS331N NDS331N PS_LED1 PS_MIO8_LED0 460 mW 460 mW UG850_c1_21_032719 Figure 1-21: User LEDs ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 47: User Pushbuttons

    Table 1-24: User Pushbutton Connections to XC7Z020 SoC U1 XC7Z020 SoC (U1) Pin Net Name I/O Standard Pushbutton and Pin Reference GPIO_SW_N LVCMOS25 SW5.3 (Left switch) GPIO_SW_S LVCMOS25 SW7.3 (Right switch) ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 48: Gpio Dip Switch

    GPIO DIP switch connections to XC7Z020 SoC U1. Table 1-25: GPIO DIP Switch Connections to XC7Z020 SoC at U1 XC7Z020 (U1) Pin Net Name I/O Standard DIP Switch SW12 Pin GPIO_DIP_SW0 LVCMOS25 GPIO_DIP_SW1 LVCMOS25 ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 49: User Ps Switches

    SW14.4 and SW15.2 User PMOD GPIO Headers [Figure 1-2, callout 28] The ZC702 board supports two GPIO headers J62 and J63. The PMOD nets connected to these headers are dual-purpose, with the User LEDs wired in parallel to the header pins.
  • Page 50 UG850_c1_25_030513 Figure 1-25: User GPIO Headers When using the PMOD headers on the Zynq-7000 SoC ZC702 evaluation kit, the voltage level output might appear normal at steady state; however, the rise and fall times on the other side of the TXS0108E level shifters can be several microseconds. The paralleled LED driver NDS331N FET has a gate capacitance of ~200 pF.

  • Page 51: Switches

    Do NOT plug a PC ATX power supply 6-pin connector into J60 on the ZC702 board. The ATX CAUTION! 6-pin connector has a different pinout than J60. Connecting an ATX 6-pin connector into J60 damages the ZC702 board and voids the board warranty.

  • Page 52: Program_B Pushbutton

    7 series FPGAs. Figure 1-27 shows SW4. X-Ref Target - Figure 1-27 VCC2V5 4.7kΩ 0.1 Ω To XC7Z020 SoC FPGA PROG B PROGRAM_B_0 (U1.T11) UG850_c1_27_032719 Figure 1-27: PROG_B Pushbutton SW4 ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 53: Ps Power-On And System Reset Pushbuttons

    This reset is used to force a system reset. It can be tied or pulled High, and can be PS_SRST_B: High during the PS supply power ramps. Refer to the Zynq-7000 SoC Technical Reference Manual [Ref 2] for information (UG585) concerning the resets. ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 54: Fpga Mezzanine (Fmc) Card Interface

    (LPC) connectors at J3 and J4. Both connectors use a 10 x 40 form factor that is partially populated with 160 pins. The connectors are keyed so that a the mezzanine card faces away from the ZC702 board when connected.
  • Page 55 FMC1_LPC_LA03_P LVCMOS25 FMC1_LPC_LA02_P LVCMOS25 FMC1_LPC_LA03_N LVCMOS25 FMC1_LPC_LA02_N LVCMOS25 FMC1_LPC_LA08_P LVCMOS25 FMC1_LPC_LA04_P LVCMOS25 FMC1_LPC_LA08_N LVCMOS25 FMC1_LPC_LA04_N LVCMOS25 FMC1_LPC_LA12_P LVCMOS25 FMC1_LPC_LA07_P LVCMOS25 FMC1_LPC_LA12_N LVCMOS25 FMC1_LPC_LA07_N LVCMOS25 FMC1_LPC_LA16_P LVCMOS25 FMC1_LPC_LA11_P LVCMOS25 ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...
  • Page 56 FMC1_LPC_LA24_P LVCMOS25 FMC1_LPC_LA29_N LVCMOS25 FMC1_LPC_LA24_N LVCMOS25 FMC1_LPC_LA31_P LVCMOS25 FMC1_LPC_LA28_P LVCMOS25 FMC1_LPC_LA31_N LVCMOS25 FMC1_LPC_LA28_N LVCMOS25 FMC1_LPC_LA33_P LVCMOS25 FMC1_LPC_LA30_P LVCMOS25 FMC1_LPC_LA33_N LVCMOS25 FMC1_LPC_LA30_N LVCMOS25 VADJ FMC1_LPC_LA32_P LVCMOS25 FMC1_LPC_LA32_N LVCMOS25 VADJ ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...
  • Page 57 GA0 = 0 = GND FMC2_LPC_LA26_N LVCMOS25 U11 VCC12_P FMC2_LPC_TCK_BUF VCC12_P FMC1_LPC_TDO_FMC 2_LPC_TDI VCC3V3 FMC2_LPC_TDO_FPG A_TDI VCC3V3 FMC2_LPC_TMS_BUF GA0 = 0 = GND VCC3V3 VCC3V3 VCC3V3 FMC2_LPC_CLK1_M2C_P LVCMOS25 ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...
  • Page 58 LVCMOS25 AB10 FMC2_LPC_LA28_P LVCMOS25 AB5 FMC2_LPC_LA31_N LVCMOS25 FMC2_LPC_LA28_N LVCMOS25 AB4 FMC2_LPC_LA33_P LVCMOS25 FMC2_LPC_LA30_P LVCMOS25 AB7 FMC2_LPC_LA33_N LVCMOS25 FMC2_LPC_LA30_N LVCMOS25 AB6 VADJ FMC2_LPC_LA32_P LVCMOS25 Y4 FMC2_LPC_LA32_N LVCMOS25 AA4 VADJ ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 59: Power Management

    1-2, callout 25] TheZC702 PCB layout and power system design meets the recommended criteria described in the Zynq-7000 SoC PCB Design Guide (UG933) [Ref 13]. The ZC702 board power distribution diagram is shown in Figure 1-29. ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...
  • Page 60 PMBus Addr 0b0110110 Switching Regulator VCC3V3 3.3V at 10A VCC2V5 Switching Regulator 2.5V at 10A Linear Regulator VTTDDR 0.75V at 3A VREF UG850_c1_29_090215 Figure 1-29: Onboard Power Regulators ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...
  • Page 61 Feature Descriptions The ZC702 board uses power regulators and a PMBus compliant system controller from Texas Instruments to supply core and auxiliary voltages as listed in Table 1-30. The Texas Instruments Fusion Digital Power graphical user interface is used to monitor the voltage and current levels of the board power modules.

  • Page 62: Vadj Voltage Control

    Low by the user logic and the VADJ rail comes up at the new VADJ voltage level. Installing a jumper at J12 after a ZC702 board powers up in this mode turns on the VADJ rail. The FMC_VADJ_ON_B signal is sourced by the TCA6416APWR I2C port expander U80 pin 13...
  • Page 63 1.15 Notes: 1. The values defined in these columns are the voltage, current, and temperature thresholds that causes the regulator to shut down if the value is exceeded. ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 64: Cooling Fan

    1-30. X-Ref Target - Figure 1-30 VCC12_P UG850_c1_30_030513 Figure 1-30: Cooling Fan Circuit More information about the power system components used by the ZC702 board are available from the Texas Instruments digital power website [Ref 25]. ZC702 Board User Guide www.xilinx.com...

  • Page 65: Xadc Analog-To-Digital Converter

    100Ω UG850_c1_31_031819 Figure 1-31: XADC Block Diagram The ZC702 board supports both the internal XC7Z020 SoC sensor measurements and the external measurement capabilities of the XADC. Internal measurements of the die temperature, VCCINT, VCCAUX, and VCCBRAM are available. ZC702 Board User Guide www.xilinx.com...
  • Page 66 Digital I/O. These pins should come from the same bank. These I/Os XADC_GPIO_3, 2, 1, 0 19, 20, 17, 18 should not be shared with other functions because they are required to support 3-state operation. ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 67: Appendix A: Default Switch And Jumper Settings

    Position Setting Callout SW10 (JTAG chain input select two-position DIP switch) SW12 (two-position DIP switch) SW15 (two-position DIP switch) Right Right SW16 Right (five-position DIP switch) Right Right ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 68: Jumpers

    Jumper Function Default Position HDR_1 X 2 CFGBVS short to GND ZC702 configuration bank 0 is operated at 2.5V, therefore the CFGBVS pin is pulled high with a resistor. Jumper J5 should be never installed. POR Master Reset USB 2.0 USB_VBUS_SEL...
  • Page 69 ETHERNET PHY HDR NONE USB 2.0 MODE USB 2.0 J1 ID SEL USB 2.0 J1 VBUS CAP SEL USB 2.0 J1 GND SEL XADC_VREP SEL XADC_VCC SEL XADC_VREF SOURCE SEL ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...
  • Page 70 Jumpers Figure A-1 shows jumper locations described in this table. X-Ref Target - Figure A-1 22 23 18 17 19 20 UG850_a1_01_011415 Figure A-1: Jumper Locations ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 71: Appendix B: Vita 57.1 Fmc Connector Pinouts

    Figure B-1 shows the pinout of the FPGA mezzanine card (FMC) low pin count (LPC) connector defined by the VITA 57.1 FMC specification. For a description of how the ZC702 board implements the FMC specification, see FPGA Mezzanine (FMC) Card Interface...

  • Page 72: Appendix C: Xilinx Design Constraints

    The ZC702 Xilinx® Design Constraints (XDC) template provides for designs targeting the ZC702 board. Net names in the constraints correlate with net names on the latest ZC702 board schematic. You must identify the appropriate pins and replace the net names below with net names in your RTL.

  • Page 73: Appendix D: Board Specifications

    Width: 7.750 in. (19.685 cm) Length: 7.150 in. (18.161 cm) Environmental Temperature Operating: 0°C to +45°C Storage: –25°C to +60°C Humidity 10% to 90% non-condensing Operating Voltage +12 V ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

  • Page 74: Appendix E: Regulatory And Compliance Information

    This product is designed and tested to conform to the European Union directives and standards described in this section. Refer to the ZC702 board master answer record concerning the CE requirements for the PC Test Environment: ZC702 Evaluation Kit – Master Answer Record 47864 Zynq-7000 ZC702 Declaration of Conformity is online.

  • Page 75: Safety

    Xilinx has met its national obligations to the EU WEEE Directive by registering in those countries to which Xilinx is an importer. Xilinx has also elected to join WEEE Compliance Schemes in some countries to help manage customer returns at end-of-life.
  • Page 76 Topics include design assistance, advisories, and troubleshooting tips. References The most up to date information related to the ZC702 board and its documentation is available on the following websites. ZC702 Evaluation Kit ZC702 Evaluation Kit –...
  • Page 77 (RTC-8564JE) 23. Digilent: www.digilentinc.com www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9 (Pmod Peripheral Modules) 24. NXP Semiconductors: ics.nxp.com (TJA01040) 25. Texas Instruments: www.ti.com, www.ti.com/fusiondocs, www.ti.com/ww/en/analog/digital-power/index.html and (UCD9248PFC, PTD08A010W, PTD08A020W, PTD08D210W, LMZ12002, TL1962ADC, TPS51200DR, PCA9548) ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...
  • Page 78 26. Texas Instruments EVM USB-TO-GPIO: www.ti.com/xilinx_usb. 27. Texas Instruments TI Fusion Digital Power Designer GUI, downloadable from: http://www.ti.com/fusion-gui 28. Samtec: www.samtec.com. (SEAF series connectors) 29. Integrated Device Technology: www.idt.com (ICS844021I) ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.7) March 27, 2019...

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