Ethernet Phy Clock Source - Xilinx ZC706 User Manual

Table 1-19: Board Connections for PHY Configuration Pins
U51 Pin
CONFIG (64)
CONFIG1 (1)
CONFIG2 (2)
CONFIG3 (3)
The Ethernet connections from the XC7Z045 AP SoC at U1 to the 88E1116R PHY device at
U51 are listed in
Table 1-20: Ethernet Connections, XC7Z045 AP SoC to the PHY Device
XC7Z045 (U1) Pin
Pin Name
PS_MIO53
PS_MIO52
PS_MIO16
PS_MIO21
PS_MIO20
PS_MIO19
PS_MIO18
PS_MIO17
PS_MIO22
PS_MIO27
PS_MIO26
PS_MIO25
PS_MIO24
PS_MIO23

Ethernet PHY Clock Source

A 25.00 MHz 50 ppm crystal at X1 is the clock source for the 881116R PHY at U51.
Figure 1-20 shows the clock source.
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
Setting Configuration
VCCP1V8 PHYAD[1]=1
PHY_LED0 PHYAD[3]=0
GND ENA_XC=0
PHY_LED0 ENA_XC=0
VCCP1V8 ENA_XC=1
GND RGMII_TX=0
PHY_LED0 RGMII_TX=0
PHY_LED1 RGMII_TX=1
VCCP1V8 RGMII_TX=1
Table 1-20.
Pin
Bank
Number
501 C18
501 D19
501 L19
501 J19
501 M20
501 J20
501 K20
501 K21
501 L20
501 G20
501 M17
501 G19
501 M19
501 J21
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PHYAD[0]=1
PHYAD[2]=1
PHYAD[4]=0
PHYAD[4]=1
PHYAD[4]=1
RGMII_RX=0
RGMII_RX=1
RGMII_RX=0
RGMII_RX=1
M88E1116R PHY U51
Schematic
Net Name
Pin
PHY_MDIO 45
PHY_MDC 48
PHY_TX_CLK 60
PHY_TX_CTRL 63
PHY_TXD3 62
PHY_TXD2 61
PHY_TXD1 59
PHY_TXD0 58
PHY_RX_CLK 53
PHY_RX_CTRL 49
PHY_RXD3 55
PHY_RXD2 54
PHY_RXD1 51
PHY_RXD0 50
Feature Descriptions
Name
MDIO
MDC
TX_CLK
TX_CTRL
TXD3
TXD2
TXD1
TXD0
RX_CLK
RX_CTRL
RXD3
RXD2
RXD1
RXD0
48
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