Xilinx ZC706 User Manual page 19

Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 AP SoC (Cont'd)
XC7Z045 (U1)
Pin
D6
B7
H12
A10
G11
C6
F8
H7
A7
L1
L2
K5
J4
K1
L3
J5
K6
G6
H4
H6
H3
G1
H2
G5
G4
E2
E3
D4
E5
F4
F3
D1
D3
A2
B2
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
Net Name I/O Standard
PL_DDR3_A10 SSTL15
PL_DDR3_A11 SSTL15
PL_DDR3_A12 SSTL15
PL_DDR3_A13 SSTL15
PL_DDR3_A14 SSTL15
PL_DDR3_A15 SSTL15
PL_DDR3_BA0 SSTL15
PL_DDR3_BA1 SSTL15
PL_DDR3_BA2 SSTL15
PL_DDR3_D0 SSTL15
PL_DDR3_D1 SSTL15
PL_DDR3_D2 SSTL15
PL_DDR3_D3 SSTL15
PL_DDR3_D4 SSTL15
PL_DDR3_D5 SSTL15
PL_DDR3_D6 SSTL15
PL_DDR3_D7 SSTL15
PL_DDR3_D8 SSTL15
PL_DDR3_D9 SSTL15
PL_DDR3_D10 SSTL15
PL_DDR3_D11 SSTL15
PL_DDR3_D12 SSTL15
PL_DDR3_D13 SSTL15
PL_DDR3_D14 SSTL15
PL_DDR3_D15 SSTL15
PL_DDR3_D16 SSTL15
PL_DDR3_D17 SSTL15
PL_DDR3_D18 SSTL15
PL_DDR3_D19 SSTL15
PL_DDR3_D20 SSTL15
PL_DDR3_D21 SSTL15
PL_DDR3_D22 SSTL15
PL_DDR3_D23 SSTL15
PL_DDR3_D24 SSTL15
PL_DDR3_D25 SSTL15
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Feature Descriptions
DDR3 SODIMM Memory J1
Pin Number Pin Name
107 A10/AP
84 A11
83 A12_BC_N
119 A13
80 A14
78 A15
109 BA0
108 BA1
79 BA2
5 DQ0
7 DQ1
15 DQ2
17 DQ3
4 DQ4
6 DQ5
16 DQ6
18 DQ7
21 DQ8
23 DQ9
33 DQ10
35 DQ11
22 DQ12
24 DQ13
34 DQ14
36 DQ15
39 DQ16
41 DQ17
51 DQ18
53 DQ19
40 DQ20
42 DQ21
50 DQ22
52 DQ23
57 DQ24
59 DQ25
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