Fmc Connector Jtag Bypass; Clock Generation - Xilinx ZC706 User Manual

Table 1-11: Switch SW4 Configuration Option Settings
Configuration Source
None
Cable Connector J3
(2)
Digilent USB-to-JTAG interface U30
JTAG (flying lead) Header J62
Notes:
1. 0 = open, 1 = closed
2. Default switch setting

FMC Connector JTAG Bypass

When an FPGA mezzanine card (FMC) is attached to HPC J37 or LPC J5 it is automatically
added to the JTAG chain through electronically controlled single-pole single-throw (SPST)
switches U32 and U31 respectively. The SPST switches are normally closed and transition to
an open state when an FMC is attached. Switch U32 adds an attached FMC to the JTAG chain
as determined by the FMC_HPC_PRSNT_M2C_B signal. Switch U31 adds an attached FMC to
the JTAG chain as determined by the FMC_LPC_PRSNT_M2C_B signal. The attached FMC
card must implement a TDI-to-TDO connection through a device or bypass jumper for the
JTAG chain to be completed to the AP SoC U1.
The JTAG connectivity on the ZC706 board allows a host computer to download bitstreams
to the AP SoC using the Xilinx® iMPACT software. In addition, the JTAG connector allows
debug tools such as the Vivado serial I/O analyzer or a software debugger to access the
SoC. The iMPACT software tool can also indirectly program the linear QSPI flash memory. To
accomplish this, the iMPACT software configures the SoC with a temporary design to access
and program the QSPI memory device.

Clock Generation

[Figure 1-2, callouts 7, 8, and 9]
The ZC706 evaluation board provides four clock sources for the XC7Z045 AP SoC.
Table 1-12 lists the source devices for each clock.
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
DIP Switch SW4
(1)
Switch 1 JTAG_SEL_1
0
1
0
1
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Feature Descriptions
(1)
Switch 2 JTAG_SEL_2
0
0
1
1
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