Xilinx ZC706 User Manual page 76

Figure 1-34 shows the XADC external MUX block diagram.
X-Ref Target - Figure 1-34
Notes:
1. _XADC_P/N = Remote Voltage Sense
2. _XADC_CS_P/N = Current Sense From OP Amp
U1
49.9
ADIP L13
10PF
49.9
AD1N K13
XC7Z045
Bank 35
U16
A0
P14 17
A1
P15 18
A2
P16 19
TCA6416APWR
12C Port
Expander
See Table 1-35
details for the external MUX U6.
Table 1-35: XADC Measurements through MUX U6
Meas. Current
Rail Name
Type Range
V VCCINT
I VCCINT CS 0A-8A
V VCCAUX
I VCCAUX CS 0A-4A
V VCC1V5_PL
I VCC1V5_PL CS 0A-2A
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
U6
ADG707BRU
VCCINT_XADC_CS_P/N
S1A/B
VCCAUX_XADC_CS_P/N
S2A/B
VCC1V5_PL_XADC_P/N
S3A/B
VCC1V5_PL_XADC_CS_P/N
DA S4A/B
VADJ_FPGA_XADC_P/N
S5A/B
DB
VADJ_FPGA_XADC_CS_P/N
S6A/B
VCC3V3_PL_XADC_P/N
S7A/B
VCC3V3_PL_XADC_CS_P/N
S8A/B
A[2:0]
Figure 1-34: XADC External MUX Block Diagram
which lists the ZC706 XADC power system voltage and current measurement
Isense Op Amp
Reference
Gain
Designator
NA NA NA
U69 20
NA NA NA
U68 50
NA VCC1V5_PL REMOTE SENSE DIVIDED
TO DELIVER 0.75V ON
VCC1V5_PL_XADC_P
U67 100
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VADJ 2.5V Scaled to 0.625V
Schematic Net Name
Vo Range
NA XADC INTERNAL
0V-0.8V VCCINT_XADC_CS_P
VCCINT_XADC_CS_N
NA XADC INTERNAL
0V-1V VCCAUX_XADC_CS_P
VCCAUX_XADC_CS_N
VCC1V5_PL_XADC_P
VCC1V5_PL_SENSE_N
0V-1V VCC1V5_PL_XADC_CS_P
VCC1V5_PL_XADC_CS_N
Feature Descriptions
VCC3V3_FPGA_SENSE_P
3.01K
VCC3V3_FPGA_XADC_P
Scaled to 0.75V
1.00K
VCC3V3_FPGA_SENSE_N
GND
VCC3V3_FPGA_SENSE_P
3.01K
VCC3V3_FPGA_XADC_P
1.00K
VCC3V3_FPGA_SENSE_N
GND
VCC3V3_FPGA_SENSE_P
3.01K
VCC3V3_FPGA_XADC_P
3.3 Scaled to 0.825V
1.00K
VCC3V3_FPGA_SENSE_N
GND
UG954_c1_34_041113
8-to-1 MUX U6
MUX A[2:0]
Pin Pin
Num Name
NA NA NA
19 S1A 000
11 S1B
NA NA NA
20 S2A 001
10 S2B
21 S3A 010
9 S3B
22 S4A 011
8 S4B
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